Previous investigations on the patterning mechanism of nanoparticle photoresists provided insight into ligand displacement exerting a controlling influence on dissolution behavior of nanoparticles in organic developers. Nanoparticle core-ligand interaction which dictates ligand displacement would ultimately translate to the sensitivity of the photoresist. The current study investigates enhancement of resist sensitivity via altering the core-ligand interaction of the nanoparticle, which further emphasizes our proposed patterning hypothesis.
We have studied the photolysis of tin clusters of the type [(RSn)<sub>12</sub>O<sub>14</sub>(OH)<sub>6</sub>] X<sub>2</sub> using extreme ultraviolet (EUV,
13.5 nm) light, and developed these clusters into novel high-resolution photoresists. A thin film of
[(BuSn)<sub>12</sub>O<sub>14</sub>(OH)<sub>6</sub>][p-toluenesulfonate]<sub>2</sub> (1) was prepared by spin coating a solution of (1) in 2-butanone onto a silicon
wafer. Exposure to EUV light caused the compound (1) to be converted into a substance that was markedly less soluble
in aqueous isopropanol. To optimize the EUV lithographic performance of resists using tin-oxo clusters, and to gain
insight into the mechanism of their photochemical reactions, we prepared several compounds based on
[(RSn)<sub>12</sub>O<sub>14</sub>(OH)<sub>6</sub>] X<sub>2</sub>. The sensitivity of tin-oxide films to EUV light were studied as a function of variations in the
structure of the counter-anions (X, primarily carboxylates) and organic ligands bound to tin (R). Correlations were
sought between the EUV sensitivity of these complexes vs. the strength of the carbon-carboxylate bonds in the counteranions
and vs. the strength of the carbon-tin bonds. No correlation was observed between the strength of the carboncarboxylate
bonds in the counter-anions (X) and the EUV photosensitivity. However, the EUV sensitivity of the tinoxide
films appears to be well-correlated with the strength of the carbon-tin bonds. We hypothesize this correlation
indicates a mechanism of carbon-tin bond homolysis during exposure. Using these tin clusters, 18-nm lines were printed
showcasing the high resolution capabilities of these materials as photoresists for EUV lithography.
We present the synthesis and preliminary lithographic evaluation of Molecular Organometallic
Resists for EUV (MORE) that contain post transition metals. These post transition metal nuclei have high
EUV optical density so they can utilize a high fraction of the incident photons. We will describe two
technical approaches for EUV resist platforms that contain bismuth. Approach 1: Combination of
organometallic compounds with photoacid generators. Approach 2: Combination of high-oxidation state
metal-center oligomers that utilize carboxylate anions bound to the metal centers.
One of the major challenges associated with insertion of a directed self-assembly (DSA) patterning process in high volume manufacturing (HVM) is finding a non-destructive, yield-compatible, consistent critical dimension (CD) metrology process. Current CD scanning electron microscopy (CD-SEM) top-down approaches do not give the profile information for DSA patterns, which is paramount in determining the subsequent pattern transfer process (etch, for example). SEMATECH, in cooperation with some of the leaders of the metrology and DSA materials supply chain, has led an effort to address such metrology challenges in DSA. We have developed and evaluated several techniques (including a scatterometry-based method) that are potentially very attractive in determining DSA pattern profiles and have embedded bridging in such patterns without resorting to destructive cross-section imaging. We show how such processes could be fine-tuned to enable their insertion for DSA pattern characterization in an HVM environment.
The ability to incorporate topographic and other effects of previously patterned layers in ground rule formulation could potentially lead to significant cost savings and shortened time needed for technology ramp-up. The effect of topgraphy coupled with the diminishing depth of focus (DOF) associated with design node shrinks could become a significant yield detractor. With migration of transistor architecture from planer CMOS to 3-D FINFETs, such topographic effect could potentially pose a major challenge for future EUV processes even with significantly lower NA (Numerical Aperture) compared to current immersion DUV processes. We review how resist parameters for a given layer can be optimized to minimize imaging artifacts caused by underlying topography of previous layers. We also demonstrate how residual effects after resist parameter optimization could be handled by a sets of interlayer groundrules or novel OPC methods. Initially we study standard immersion ArF processing, then we extend the methodology to evaluate the potential issues with EUV lithography in the presence of topography. We compare the the nature and magnitude of the topography effects of such results with DUV imaging and show how we can design a new resist system to minimize such effects. We also show how future ground rule development might need to incorporate the layout information of the previously patterned layers.
This paper demonstrates a new simulation-based methodology for optimizing critical dimension (CD) bias for contact holes (CH) arrays using several different extreme ultraviolet (EUV) resists that were fully calibrated and verified with physical resist models. The bias for CH was optimized using local CD uniformity (CDU) 3-sigma as a cost function. The CD sigma variations of near-neighbor contact holes were simulated as a function of dose-to-size and mask bias, averaged over a large number of stochastic trials. There is a distinct bias for minimum CD sigma accompanied by an increase in the process window. The results are confirmed with wafer data. We will discuss the results in terms of EUV photon shot noise coupled with resist parameters. The simulation results will be used to predict a parameter space for EUV resist that can optimize line edge roughness (LER)/resolution/process window and CDU. Finally, various tradeoffs will be presented that will enable the process to perform in a high volume manufacturing environment.
During exposure in an EUV scanner, photoresist and other materials coated on a wafer are known to outgas various species. As a requirement to pattern materials in an ASML NXE scanner, these materials need to be screened for outgassing and possible optics contamination. As part of the testing process, a resist-coated wafer is exposed in a vacuum chamber mimicking the conditions inside an EUV scanner. The resist exposure source can be either EUV photons or electron beam (e-beam). This presentation will cover the results to date on a SEMATECH program to study resist outgassing from both the commercial system from EUV Tech and a custom Resist Outgassing and Exposure (ROX) tool. The EUV Tech results reported will be based on electron exposures of the photoresist, and the ROX results reported will be based on EUV photon exposures of the photoresist. The results reported will cover both tools and the measurements of over 80 commercial photoresists.
The ability to incorporate the effect of patterned underlayers in a 3-dimensional physical resist model that
truly mimics the process on real wafers could be used to formulate robust ground rules for design. We have
shown as an example block level simulations, where the resist critical dimension is determined by the
presence of STI (shallow trench isolation) and/or patterned gate level underneath & their relative spacing,
as confirmed on wafer. We will demonstrate how the results of such study could be used for creating
ground rules which are truly dependent on the interaction between the current layer resist & the patterned
layers underneath. We have also developed a new way to visualize lithographic process variations in 3-D
space that is useful for simulation analysis that can prove very helpful in ground rule development and
process optimization. Such visualization capability in the dataprep flow to flag issues or dispose critical
structures increases speed and efficiency in the mask tapeout process.
The ever-shrinking lithography process window dictates that we maximize our process window, minimize process variation, and quantify the disturbances to an imaging process caused upstream of the imaging step. Relevant factors include across-wafer and wafer-to-wafer film thickness variation, wafer flatness, wafer edge effects, and design-induced topography. We present our effort to predict design-induced focus error hot spots based on prior knowledge of the wafer surface topography. This knowledge of wafer areas challenging the edge of our process window enables a constructive discussion with our design and integration team to prevent or mitigate focus error hot spots upstream of the imaging process.
To reduce cost, implant levels usually use masks fabricated with older generation mask tools, such
as laser writers, which are known to introduce significant mask errors. In fact, for the same implant
photolithography process, Optical Proximity Correction (OPC) models have to be developed
separately for the negative and positive mask tones to account for the resulting differences from the
mask making process. However, in order to calibrate a physical resist model, it is ideal to use single
resist model to predict the resist performance under the two mask polarities. In this study, we show
our attempt to de-convolute mask error from the Correct Positive (CP) and Correct Negative (CN)
tone CD data collected from bare Si wafer and derive a single resist model. Moreover, we also
present the predictability of this resist model over a patterned substrate by comparing simulated
CD/profiles against wafer data of various features.
In this paper we will demonstrate how a 3D physical patterning model can act as a forensic tool for OPC
and ground-rule development. We discuss examples where the 2D modeling shows no issues in printing
gate lines but 3D modeling shows severe resist loss in the middle. In absence of corrective measure, there is
a high likelihood of line discontinuity post etch. Such early insight into process limitations of prospective
ground rules can be invaluable for early technology development. We will also demonstrate how the root
cause of broken poly-line after etch could be traced to resist necking in the region of STI step with the help
of 3D models. We discuss different cases of metal and contact layouts where 3D modeling gives an early
insight in to technology limitations. In addition such a 3D physical model could be used for early resist evaluation and selection for required ground-rule challenges, which can substantially reduce the cycle time for process development.
In this paper, we report large scale three-dimensional photoresist model calibration and validation
results for critical layer models that span 32 nm, 28 nm and 22 nm technology nodes. Although
methods for calibrating physical photoresist models have been reported previously, we are unaware
of any that leverage data sets typically used for building empirical mask shape correction models. .
A method to calibrate and verify physical resist models that uses contour model calibration data sets
in conjuction with scanning electron microscope profiles and atomic force microscope profiles is
discussed. In addition, we explore ways in which three-dimensional physical resist models can be
used to complement and extend pattern hot-spot detection in a mask shape validation flow.
The ever shrinking lithography process window requires us to maximize our process window and minimize tool-induced
process variation, and also to quantify the disturbances to an imaging process caused upstream of the imaging step.
Relevant factors include across-wafer and wafer-to-wafer film thickness variation, wafer flatness, wafer edge effects,
and design-induced topography. We quantify these effects and their interactions, and present efforts to reduce their harm
to the imaging process. We also present our effort to predict design-induced focus error hot spots at the edge of our
process window. The collaborative effort is geared towards enabling a constructive discussion with our design team, thus
allowing us to prevent or mitigate focus error hot spots upstream of the imaging process.
In this paper, we demonstrate a new methodology for post-etch OPC modeling to compensate for effects of
underlayer seen on product wafers. Current resist-only OPC models based on data from flopdown wafers
are not always accurate enough to deliver patterning solutions with stringent critical dimension
requirements in 45/32nm technology node. Therefore it is necessary to include an etch model into the OPC
correction. Both litho and etch model were built using flopdown and integrated wafers to compensate for
topography, differential etch due to different underlayer substrate based on local geometry and local
loading. The wafer data based on such OPC keyword show significant decrease of critical dimensions
offsets of device macros from long poly-line nested structures for gate level. We will compare wafer data
from two different OPC model versions built from flopdown and integrated wafer. We will also discuss
modeling options in terms of two layer test masks for future technologies.
We present an etch-aware optical proximity correction (OPC) flow that is intended to optimize post-etch patterns
on wafer. We take advantage of resource efficient empirical etch models and a model based retargeting scheme
to determine post-develop in-plane resist targets required to achieve post-etch critical dimensions. The goal of
this flow is to optimize final patterns on wafer rather than two independent patterns from lithography and etch.
As part of this flow, we cover important aspects of etch process variability implications for etch aware OPC.
Metrics for total pattern transfer are developed and explored with an eye toward optimizing pattern transfer.
We present results from a 45 nm poly-silicon and 32 nm shallow trench isolation levels where etch aware OPC
has been applied and compare these results with conventional resist based OPC schemes.
Finally, implications of this flow for unit process developers in lithography and reactive ion etch are explored.
We present a process optimization flow that incorporates model based retargeting into resolution enhancement
technology selection, materials selection as well as lithographic and reactive ion etch process development.
A single patterning solution is still desirable to keep the costs low for high volume wafer manufacturing. This paper will
outline the process steps necessary to scale the single patterning approach for gate level from 65mn into the 45nm
technology node. They consist mainly of the introduction of a new software for optical proximity correction, the
introduction of model based process window correction, the switch to model based etch proximity correction, and
support of an ultra dense SRAM cell. All technology requirements could be met with this single patterning solution.
The semiconductor industry faces a lithographic scaling limit as the industry completes the transition to 1.35 NA
immersion lithography. Both high-index immersion lithography and EUV lithography are facing technical
challenges and commercial timing issues. Consequently, the industry has focused on enabling double patterning
technology (DPT) as a means to circumvent the limitations of Rayleigh scaling. Here, the IBM development
alliance demonstrate a series of double patterning solutions that enable scaling of logic constructs by decoupling
the pattern spatially through mask design or temporally through innovative processes. These techniques have been
successfully employed for early 32nm node development using 45nm generation tooling. Four different double
patterning techniques were implemented. The first process illustrates local RET optimization through the use of a
split reticle design. In this approach, a layout is decomposed into a series of regions with similar imaging
properties and the illumination conditions for each are independently optimized. These regions are then printed
separately into the same resist film in a multiple exposure process. The result is a singly developed pattern that
could not be printed with a single illumination-mask combination. The second approach addresses 2D imaging
with particular focus on both line-end dimension and linewidth control . A double exposure-double etch (DE2)
approach is used in conjunction with a pitch-filling sacrificial feature strategy. The third double exposure process,
optimized for via patterns also utilizes DE2. In this method, a design is split between two separate masks such that
the minimum pitch between any two vias is larger than the minimum metal pitch. This allows for final structures
with vias at pitches beyond the capability of a single exposure. In the fourth method,, dark field double dipole
lithography (DDL) has been successfully applied to BEOL metal structures and has been shown to be overlay
tolerant . Collectively, the double patterning solutions developed for early learning activities at 32nm can be
extended to 22nm applications.
As SRAM arrays become lithographically more aggressive than random logic, they are more and more
determining the lithography processes used. High yielding, low leakage, dense SRAM cells demand fairly
aggressive lithographic process conditions. This leads to a borderline process window for logic devices.
The tradeoff obtained between process window optimization for random logic gates and dense SRAM is
not always straightforward, and sometimes necessitates design rule and layout modifications. By delinking
patterning of the logic devices from SRAM, one can optimize the patterning processes for these devices
independently. This can be achieved by a special double patterning technique that employs a combination
of double exposure and double etch (DE2). In this paper we show how a DE2 patterning process can be
employed to pattern dense SRAM cells in the 45nm node on fully integrated wafers, with more than
adequate overlap of gate line-end onto active area. We have demonstrated that this process has adequate
process window for sustainable manufacturing. For comparison purpose we also demonstrate a single
exposure single etch solution to treat such dense SRAM cells. In 45nm node, the dense SRAM cell can also
be printed with adequate tolerances and process window with single expose (SE) with optimized OPC. This
is confirmed by electrical results on wafer. We conclude that DE2 offers an attractive alternative solution to
pattern dense SRAM in 45nm and show such a scheme can be extended to 32nm and beyond. Employing
DE2 lets designers migrate to very small tip-to-tip distance in SRAM. The selection of DE2 or SE depends
on layout, device performance requirements, integration schemes and cost of ownership.
In this paper we have analyzed the ACLV performance of a 45nm CMOS logic process as a function of
gate layer exposure tool. Data from identical masks and with identical litho processes is compared side by
side on immersion and dry lithography. Theoretically, the improved focus control of immersion scanners
allows tighter CD control for pitches that have lower process windows. Thereby, the ACLV performance of
immersion lithography is expected to be better than on a comparable dry tool, when keeping all other
parameters the same. This is specifically important for foundry processes where pitches are not restricted.
The wafer results give somewhat ambivalent answers. Overall, ACLV performance of the dry tool is very
similar to the immersion tool. Taking out systematic contributions, it becomes evident that the ACLV is
dominated by dose effects and less by the curvature of the Bossung plots. Even though the focus window is
considerably smaller on the dry tool, the apparently better dose control leads to better ACLV performance
after subtracting systematic effects.
The existence of pitch range with depth of focus below a sustainable limit is a well known fact in lithography. Such
'forbidden pitch' range limits designers' ability to pack more functionality in a logic chip. One of the ways to increase
the process window is to have a careful placement of SRAFs (Sub Resolution Assist Features) that can boost process
window across the pitch range. However the standard SRAF strategy that has been followed historically is not always
able to increase the process window of these 'forbidden pitches' sufficiently to allow sustainable manufacturing. With
shrinking technology node, placement of SRAF is becoming rather difficult due to space limitations between concerned
features and mask house's ability to manufacture mask with small assist features and smaller aspect ratios. In many
cases the number of SRAF that can be inserted between main features in a symmetrical way is not enough to boost the
process window. In this paper we discuss how asymmetrical placement of SRAF can increase process window for
critical feature in layouts where such critical features are placed near not-so-critical patterns. We also discuss how such
concepts can be extended to an array of critical features, where one SRAF is placed near a critical feature instead of
placing them in the center. We finally demonstrate how wafer data confirm process window boost from such
asymmetrical placement of SRAFs in gate layer for 65nm. We also show how to determine the optimal placement of
SRAF in such cases and recommend some rules that can be used for 45nm node based on such results.
DFM (Design for Manufacturing) has become a buzzword for lithography since the 90nm node. Implementing DFM intelligently can boost yield rates and reliability in semiconductor manufacturing significantly. However, any restriction on the design space will always result in an area loss, thus diminishing the effective shrink factor for a given technology. For a lithographer, the key task is to develop a manufacturable process, while not sacrificing too much area. We have developed a high performing lithography process for attenuated gate level lithography that is based on aggressive illumination and a newly optimized SRAF placement schemes. In this paper we present our methodology and results for this optimization, using an anchored simulation model. The wafer results largely confirm the predictions of the simulations. The use of aggressive SRAF (Sub Resolution Assist Features) strategy leads to reduction of forbidden pitch regions without any SRAF printing. The data show that our OPC is capable of correcting the PC tip to tip distance without bridging between the tips in dense SRAM cells. SRAF strategy for various 2D cases has also been verified on wafer. We have shown that aggressive illumination schemes yielding a high performing lithography process can be employed without sacrificing area. By carefully choosing processing conditions, we were able develop a process that has very little restrictions for design. In our approach, the remaining issues can be addressed by DFM, partly in data prep procedures, which are largely area neutral and transparent to the designers. Hence, we have shown successfully, that DFM and effective technology shrinks are not mutually exclusive.