In this article the recent progress in the elements of EUV lithography is presented. Source power around 205W was demonstrated and further scaling up is going on, which is expected to be implemented in the field within 2017. Source availability keeps improving especially due to the introduction of new droplet generator but collector lifetime needs to be verified at each power level. Mask blank defect satisfied the HVM goal. Resist meets the requirements of development purposes and dose needs to be reduced further to satisfy the productivity demand. Pellicle, where both the high transmittance and long lifetime are demanded, needs improvements especially in pellicle membrane. Potential issues in high-NA EUV are discussed including resist, small DOF, stitching, mask infrastructure, whose solutions need to be prepared timely in addition to high-NA exposure tool to enable this technology.
Though scaling of source power is still the biggest challenge in EUV lithography (EUVL) technology era, CD and overlay controls for transistor‟s requirement are also precondition of adopting EUVL in mass production. Two kinds of contributors are identified as risks for CDU and Overlay: Infrared (IR) and deep ultraviolet (DUV) out of band (OOB) radiations from laser produced plasma (LPP) EUV source. IR from plasma generating CO2 laser that causes optics heating and wafer overlay error is well suppressed by
introducing grating on collector to diffract IR off the optical axis and is the effect has been confirmed by operation of pre-production tool (NXE3100). EUV and DUV OOB which are reflected from mask black boarder (BB) are root causes of EUV-specific CD error at the boundaries of exposed shots which would result in the problem of CDU out of spec unless sufficiently suppressed. Therefore, control of DUV OOB reflection from the mask BB is one of the key technologies that must be developed prior to EUV mass production. In this paper, quantitative assessment on the advantage and the disadvantage of potential OOB solutions will be discussed. EUV and DUV OOB impacts on wafer CDs are measured from NXE3100 & NXE3300
experiments. Significant increase of DUV OOB impact on CD from NXE3300 compared with NXE3100 is observed. There are three ways of technology being developed to suppress DUV OOB: spectral purity filter (SPF) as a scanner solution, multi-layer etching as a solution on mask, and resist top-coating as a process solution. PROs and CONs of on-scanner, on-mask, and on-resist solution for the mass production of EUV lithography will be discussed.
As the International Technology Roadmap for Semiconductors critical dimension uniformity (CDU) specification shrinks, semiconductor companies need to maintain a high yield of good wafers per day and high performance (and hence market value) of finished products. This cannot be achieved without continuous analysis and improvement of on-product CDU as one of the main drivers for process control and optimization with better understanding of main contributors from the litho cluster: mask, process, metrology and scanner. We will demonstrate a study of mask CDU characterization and its impact on CDU Budget Breakdown (CDU BB) performed for advanced extreme ultraviolet (EUV) lithography with 1D (dense lines) and 2D (dense contacts) feature cases. We will show that this CDU contributor is one of the main differentiators between well-known ArFi and new EUV CDU budgeting principles. We found that reticle contribution to intrafield CDU should be characterized in a specific way: mask absorber thickness fingerprints play a role comparable with reticle CDU in the total reticle part of the CDU budget. Wafer CD fingerprints, introduced by this contributor, may or may not compensate variations of mask CDs and hence influence on total mask impact on intrafield CDU at the wafer level. This will be shown on 1D and 2D feature examples. Mask stack reflectivity variations should also be taken into account: these fingerprints have visible impact on intrafield CDs at the wafer level and should be considered as another contributor to the reticle part of EUV CDU budget. We also observed mask error enhancement factor (MEEF) through field fingerprints in the studied EUV cases. Variations of MEEF may play a role towards the total intrafield CDU and may need to be taken into account for EUV lithography. We characterized MEEF-through-field for the reviewed features, with results herein, but further analysis of this phenomenon is required. This comprehensive approach to quantifying the mask part of the overall EUV CDU contribution helps deliver an accurate and integral CDU BB per product/process and litho tool. The better understanding of the entire CDU budget for advanced EUVL nodes achieved by Samsung and ASML helps extend the limits of Moore’s Law and to deliver successful implementation of smaller, faster and smarter chips in semiconductor industry.
As the ITRS Critical Dimension Uniformity (CDU) specification shrinks, semiconductor companies need to maintain a
high yield of good wafers per day and a high performance (and hence market value) of finished products. This cannot be
achieved without continuous analysis and improvement of on-product CDU as one of the main drivers for process
control and optimization with better understanding of main contributors from the litho cluster: mask, process, metrology
In this paper we will demonstrate a study of mask CDU characterization and its impact on CDU Budget Breakdown
(CDU BB) performed for an advanced EUV lithography with 1D and 2D feature cases.
We will show that this CDU contributor is one of the main differentiators between well-known ArFi and new EUV CDU
budgeting principles. We found that reticle contribution to intrafield CDU should be characterized in a specific way:
mask absorber thickness fingerprints play a role comparable with reticle CDU in the total reticle part of the CDU budget.
Wafer CD fingerprints, introduced by this contributor, may or may not compensate variations of mask CD’s and hence
influence on total mask impact on intrafield CDU at the wafer level. This will be shown on 1D and 2D feature examples
in this paper.
Also mask stack reflectivity variations should be taken into account: these fingerprints have visible impact on intrafield
CDs at the wafer level and should be considered as another contributor to the reticle part of EUV CDU budget.
We observed also MEEF-through-field fingerprints in the studied EUV cases. Variations of MEEF may also play a role
for the total intrafield CDU and may be taken into account for EUV Lithography. We characterized MEEF-through-field
for the reviewed features, the results to be discussed in our paper, but further analysis of this phenomenon is required.
This comprehensive approach to characterization of the mask part of EUV CDU characterization delivers an accurate
and integral CDU Budget Breakdown per product/process and Litho tool.
The better understanding of the entire CDU budget for advanced EUVL nodes achieved by Samsung and ASML helps to
extend the limits of Moore's Law and to deliver successful implementation of smaller, faster and smarter chips in
38nm half pitch pattern was replicated from Si master pattern to quartz blank template. It is a novel approach different
from typical quartz to quartz replication. This replication concept is expected to alleviate the burden not only in cost but
also resolution for NIL template fabrication. In this study, full field Si master fabricated by ArF immersion lithography,
UV-transparent hard mask for quartz blank template and core-out quartz blank template were applied to prove the
concept. And the replica template was evaluated with NIL and subsequent etching.
EUV lithography is one of the most promising technologies for the fabrication of beyond 30nm HP generation devices.
However, it is well-known that EUV lithography still has significant challenges. A great concern is the change of resist
material for EUV resist process. EUV resist material formulations will likely change from conventional-type materials.
As a result, substrate dependency needs to be understood.
TEL has reported that the simulation combined with experiments is a good way to confirm the substrate dependency. In
this work the application of HMDS treatment and SiON introduction, as an underlayer, are studied to cause a footing of
resist profile. Then, we applied this simulation technique to Samsung EUV process. We will report the benefit of this
simulation work and effect of underlayer application.
Regarding the etching process, underlayer film introduction could have significant issues because the film that should be
etched off increases. For that purpose, thinner films are better for etching. In general, thinner films may have some
coating defects. We will report the coating coverage performance and defectivity of ultra thin film coating.
Extreme ultraviolet lithography (EUVL) is the most effective way to print sub-30 nm features. The roughness of both the
resist sidewall (line width roughness [LWR]) and resist top must be overcome soon for EUVL to be implemented.
Currently, LWR can vary by about 1 nm according to the recipe used. We have characterized two promising techniques
to improve LWR, an EUV rinse/TBAH process and an implant process, and demonstrated their efficacy. After cleaning
inspection (ACI), LWR was improved with both the rinse and implant processes. After development inspection (ADI),
LWR improved (0.12 nm, 2.4%) and ACI LWR improved (0.1 nm, 2.0% improvement) after using the EUV rinse
process. ADI and ACI LWR improvement (0.45 nm, 9.1%, and 0.3 nm, 6.9%, respectively) was demonstrated with the
EUV rinse/TBAH process. ADI LWR improvement (0.5 nm, 8.1%) and ACI LWR improvement (-0.5 nm, -16.9%) were
characterized with the implant process. Critical dimension (CD) showed similar changes through pitch after the EUV
rinse or TBAH process, but the degree of change depended on the initial pattern size giving CD difference of 2 nm
between 30 nm HP and 50 nm HP after the implant process. For this technique, the dependence of CD change on pattern
size must be minimized. Further extensive studies with rinse or implant are strongly encouraged for continued LWR
improvement and real process implementation in EUVL. Demonstrating <2.2 nm LWR after pattern transfer is important
in EUVL and needs to be pursued using various technical approaches.
Initial resist LWR is important in assessing LWR improvements with additional process techniques. An initial EUV
LWR < ~5.0 nm is required to properly assess the validity of the technique. Further study is required to improve ADI
LWR and maintain better LWR after etch with advanced EUV rinse materials. Defects also need to be confirmed
following the EUV rinse and TBAH developer. Further developing the implant process should focus on LWR
improvement at low frequencies and optimization of process conditions to maintain the EUV resist profile and resist
height. The dependence of CD change on pattern size likewise needs to be minimized.
Extreme ultra violet (EUV) resists have been developed to be able to print sub-30nm L/S features with EUV alpha
DEMO tool (ADT) having 0.25NA. However, a lithographic performance of EUV resist is not comparable to that of
DUV resist. At same process constant (k1), the imaging capability of EUV resist is poor than that of DUV resists. The
most critical issues are line width roughness (LWR) and critical dimension (CD) variation across a field. Although there
are many studies to improve the LWR of EUV resist, the issue on CD variation across a field is not much explored,
because the problem can be detected at full field exposure. In this paper, sources of the CD variation across a field are
mainly investigated, and solutions to improve the CD uniformity are explored. Out of band (OOB) radiation and its
reflectivity at REticle MAsking (REMA) unit of scanner or absorber of mask is regarded as one of the sources which
aggravates imaging quality of EUV resist. In addition, the optical density of black border at EUV wavelength is also
known to have an impact on this CD variation. Although the exact spectrum of OOB radiation is not open, LASER
produced plasma (LPP) type source and discharge produced plasma (DPP) type source are believed to have the OOB
radiation. Therefore, to improve pattern fidelity and LWR of EUV resist, the mitigation of OOB radiation impact is
required. It is found that the resist sensitivity to DUV compared to EUV is important, and this property affects on CD
uniformity. Furthermore, new material which can mitigate the OOB radiation impact is developed. This material is
applied as an additional layer on conventional EUV resist film, and shows no intermixing. Process window is not
changed by applying this layer. The filtering ability of OOB radiation is explored. LWR and pattern fidelity are much
improved by applying this material to EUV process.
Patterning of sub-30 nm features using high resolution nano-imprint lithography (NIL) requires use of quartz
templates. To this end, various fabrication methods such as e-beam lithography, edge lithography, and focused ion beam
lithography were employed for the template formation. Despite significant advances using these methods, NIL
template formation process suffers from low throughput and high cost of fabrication when compared with the fabrication
of masks used in optical lithography. This is largely owing to a 4X difference in feature sizes involved for the
fabrication of NIL template and optical lithography mask. In this paper, we report on a simple, cost-effective method for
the fabrication of sub-30 nm NIL templates. Typical fabrication-time required for the formation of sub-30 nm HP
templates using conventional Gaussian beam electron beam lithography, runs into several days. Additionally, complicated
etch procedures must be employed for pattern transfer onto quartz substrates. Here we propose a low cost, simplified
fabrication process for the formation of high resolution NIL templates using wafer pattern replication. We fabricated sub-
30nmHP poly-silicon lines and spaces on silicon wafer using multiple patterning technique. These patterns were subsequently
transferred onto quartz substrates using NIL technique.
Several types of features were studied to realize a template using the triple patterning technique described above. Results of wafer printing using the said template will be discussed.
Proc. SPIE. 7636, Extreme Ultraviolet (EUV) Lithography
KEYWORDS: Signal to noise ratio, Defect detection, Inspection, Scanning electron microscopy, Wafer inspection, Photomasks, Line width roughness, Extreme ultraviolet lithography, Line edge roughness, Semiconducting wafers
EUVL is the strongest candidate for a sub-20nm lithography solution after immersion double-patterning. There are still
critical challenges for EUVL to address to become a mature technology like today's litho workhorse, ArF immersion.
Source power and stability, resist resolution and LWR (Line Width Roughness), mask defect control and infrastructure
are listed as top issues. Source power has shown reasonably good progress during the last two years. Resist resolution
was proven to resolve 32nm HP (Half Pitch) lines and spaces with good process windows even though there are still
concerns with LWR. However, the defectivity level of blank masks is still three orders of magnitude higher than the
requirement as of today.
In this paper, mask defect control using wafer inspection is studied as an alternative solution to mask inspection for
detection of phase defects on the mask. A previous study suggested that EUVL requires better defect inspection
sensitivity than optical lithography because EUVL will print smaller defects. Improving the defect detection capability
involves not only inspection system but also wafer preparation. A few parameters on the wafer, including LWR and
wafer stack material and thickness are investigated, with a goal of enhancing the defect capture rate for after
development inspection (ADI) and after cleaning inspection (ACI). In addition to defect sensitivity an overall defect
control methodology will be suggested, involving mask, mask inspection, wafer print and wafer inspection.
EUV resists have been developed to be able to print sub-30nm L/S features with EUV ADT having 0.25NA. However, a
lithographic performance especially line width roughness (LWR) of EUV resist is not comparable to that of DUV resist.
Shot noise effect has been regarded as a main reason for this poor performance of EUV resist [1-2]. Polymer bound PAG
with sensitizer is considered as one of solutions to overcome this problem. The champion resist based on polymer bound
PAG shows good performance at 30nm L/S and 27nm L/S patterns, although LWR is still worse than target. Additional
processes such as smoothing process, chemical treatment process and surfactant rinse process are evaluated. Surfactant
rinse process which can improve LWR and pattern collapse simultaneously is regarded as a best solution. A new resist
which can overcome out-of band radiation problem is required for EUV lithography. A resist which is totally transparent
at DUV or a resist which is very opaque at DUV wavelength is expected to be a solution for OOB problem of EUV
The two key factors in EUV lithography imaging will be flare and shadow effect among other issues. The flare which is
similar to the long range density loading effect and also known to be of high level will generate CD variation throughout
the exposure field while the EUV specific shadow effect differentiates H-V CDs along the slit. The long range character
of flare in EUV full field scanner can even affect CDs in the neighboring fields. It seems to be apparent that the major
imaging challenges for EUV lithography to be successfully adopted and applied to device manufacturing will be
determined by how smartly and effectively CD variations induced both by flare and shadow effect in the full chip level
are compensated. We investigated and assessed the previously proposed full chip level compensation strategies of the
flare and shadow effect in EUVL for the application to memory device both by simulation and experiments on the
condition of full field scanner. The effectiveness of flare compensation for the case of thin absorber mask was also
addressed together with related impact on the shadow induced H-V CD bias.
Extreme ultraviolet lithography (EUVL) is one of the leading candidates for next-generation lithography technology for
the 32 nm half-pitch node and beyond. We have evaluated the Alpha Demo Tool(ADT) characterizing for mixed-andmatched
overlay(MMO), flare noise, and resolution limit. For process integration, one of the important things in EUVL
is overlay capability. We performed an overlay matching test of a 1.35NA and 193 immersion tool using a low thermal
expansion material(LTEM) mask. We also investigated the flare level of the EUV ADT for device applications. The
current EUV tool has a higher flare level than ArF lithography tools. We applied a contact layer for 40nm node device
integration to reduce the variation in critical dimension(CD) from the flare noise.
Flare in EUV mirror optics has been reported to be very high and long range effect due to its character which is inversely
proportional to the 4th order of wavelength. The high level of flare will generate CD (Critical Dimension) variation
problem in the area where the gradient of aerial pattern density is large while the long range influencing character would
confront an issue of computational challenge either for OPC (Optical Proximity Correction) modeling or for any other
practical ways to accommodate such a long range effect. There also exists another substantial challenge of measuring
and characterizing such a long range flare accurately enough so that the characterized flare can successfully be used for
the compensation in the standard OPC flow.
As VLSI products are being developed rapidly, design rules of semiconductor devices are correspondingly shrinking. Therefore, the electric couplings between adjacent lines are increasing and this phenomenon requires control of critical dimension uniformity (CDU) more tightly. In addition to that, the development of lithography tool for sub- 40nm design rule (D/R) is being delayed, which makes most IC manufacturer drive double patterning technology (DPT) as next generation lithography (NGL) solution. CD control is one of critical issues to implement DPT for mass production, because CD of 1st pattern affects the formation of 2nd pattern seriously so that the uniformity of 1st pattern is more important.
In this paper, the improvement of CD uniformity is investigated, especially for 3Xnm flash device for where double patterning technique is applied. Several methods have been considered or evaluated to improve CD uniformity. Among them, DoseMapperTM of ASML shows promising results. Using this system, in field uniformity (IFU) & in wafer uniformity (IWU) are improved 14% in 3&sgr;. To be implemented as a technology for mass production and to maintain the best performance, several efforts in terms of metrology and process will be further discussed in this paper.
Dummy contact generation procedure to apply off-axis illumination (OAI) to a contact layer in a 60 nm node device is described. The model based optical proximity correction (OPC) is also adopted to control the on-chip variation (OCV). The dummy contact size of 110 nm with the space distance of 90 nm between the main and dummy contact is used. By applying OPCed contact, the proximity variation is reduced less than 11 nm from 49 nm. The modeling methods are assessed by comparing delta edge placement error (EPE) values, which represent the model accuracy. The VTR_E model is shown to well correct the proximity variation, and it is adopted in our experiment.
Applying to the arbitrary patterns of logic device and to generate more dummy patterns, the rule needs to be modified. The modified rule includes the dummy merge method, and the dummy contacts are automatically generated for the contact layer of 60 nm node logic device.
In optical lithography, small space patterning is the most difficult task. The direct small-space patterning is not good enough with resolution enhancement technique (RET) in sub-80 nm level. Two sequential processes normally achieve the small space. Once the pattern is forming a larger pattern normally, and then makes them shrink to fit to the designed size by additional process. Usually resist thermal flow process has been used to obtain small space as additional process, which has several process issues such as flow amount control of isolated and dense small contacts, uniformity degradation and bowing profile. In order to solve these issues, we introduced the resolution enhancement lithography assisted by chemical shrink (RELACS) and shrink assist film for enhancement resolution (SAFIER) process in ArF lithography. In this paper, the RELACS and SAFIER process are compared with the resist thermal flow process for sub-80 nm space using ArF exposure tool. With the application of this process, we confirmed the improvement of in-wafer uniformity and the successful implementation of sub-80nm small space patterning regardless of pitch size and pattern arrangement.
A method of PSM cleaning has been developed and its cleaning performance was studied by changing H<sub>2</sub>SO<sub>4</sub> / H<sub>2</sub>O<sub>2</sub> mixture(SPM) and diluted standard cleaning-1 (SC-1) chemical ratio and controlling phase and transmittance of KrF HT PSM, within ±3° and ±0.3 percent respectively. The type of residue was scrutinized using KLA-Tencor SL3UV and scanning electron microscopy (SEM) during stepwise process and cleaning. X-ray photoelectron spectroscopy (XPS) was also employed to characterize the residues on the HT PSM surface. Diluted HF (DHF) and DHF/H<sub>2</sub>O<sub>2</sub> mixture (FPM) were introduced to etch off the remaining defects on quartz after MoSiON dry etch process and also compared their results with the gas assisted etching (GAE) repair. It has turned out that DHF, FPM and GAE repair removed the remaining defects on quartz respectively. Our results demonstrate that approach of stepwise process inspection is very effective at identifying defects and their sources as they become evident at different process steps. Finally it was shown that diluted SC-1 with quick dump method followed by the direct displacement IPA dry is promising for the improvement of HT PSM cleaning efficiency and its residual impurities and causes no damage on the MoSiON surface. It is found that efficient and effective conventional chemical treatment, direct displacement IPA dry and GAE repair would be considered to be the integrated sequence to control the smallest particles for the HT PSM.
For a dual layer structure, the effect of different physical geometries is studied using 0.65 and 0.85 of numerical aperture(NA), and this result gives an incitation for making a physical format for rewritable high density disc.