High intensity focused ultrasound (HIFU), has applications in treating various cancers, such as prostate, liver and breast cancer. In order for HIFU to be effective and efficient it needs to be guided by an imaging modality. While there are several options for guiding HIFU treatment, one of the most promising is ultrasound elastography. Current commercial devices use Brightness-Mode (B-mode) imaging or MRI, and are manual processes. Ultrasound elastography, allows complete automation of HIFU treatment due to the enhanced image, that elastography provides. The elastic image provides more information and less noise. To show that segmentation was possible on elastic images, nine algorithms were implemented in matlab and used on three distinct images for object detection. The three images used, have varying properties regarding object intensity and placement, as well as different noise patterns. Using PSNR, to gauge the effectiveness of each algorithm, it was shown that segmentation was possible on all images using different algorithms. The bilateral-shock-bilateral algorithm proved to be an overall effective algorithm in every situation with a PSNR of 83.87db on the phantom image. The segmentation results clearly highlight any object in the images. Future work includes fine tuning the algorithm with different phantom images and in-vivo images to distinguish between noise and desired object.
Traditional noise removal filters have an undesirable side effect of blurring edges, which is unacceptable for some image processing applications. To overcome this problem, our ongoing project evaluates an edge enhancing smoothening filter and implements it on FPGAs to reduce noise while sharpening edges. One such edge enhancing smoothing filter consists of a combination of the bilateral filter (used for edge preserving smoothing) and the Shock filter (used for edge enhancement) to achieve the desired result. This paper describes an implementation of the bilateral filter on Altera FPGAs. Shock filter part is then briefly described. Area and speed performance results for different Altera FPGA families are comparatively shown.
Rank filter is a non-linear filter used in image processing for impulse noise removal, morphological
operations, and image enhancement. Real-time applications, such as video and high-speed acquisition
cameras, often require the rank filter, and the much simpler median filter. Implementing the rank filter in
hardware, can achieve the required speeds for these applications. Bit-serial algorithm can increase the
speed of rank filter by eliminating the time-consuming sorting network. In this paper, an 8-stage pipelined
architecture for rank filter is described using the bit-serial algorithm. It also includes an efficient window
extraction and boundary-processing scheme. This rank filter design was simulated and synthesized on the
Xilinx family of FPGAs. For 3×3 window size, the maximum operating frequency achieved was 75 MHz
on a low-end device XC3S200 of Spartan-3 family, and 180 MHz on a high-end device XC4VSX25 of
Virtex-4 family. For 5×5 window size, the maximum operating frequency achieved was 67 MHz on
XC3S200, and 138 MHz on XC4VSX25. With a pixel filtered out at every clock cycle, the achieved
speeds are sufficient for most of the video applications. The 3×3 window size design used 31% of slices on
XC3S200, and 5% on XC4VSX25. The 5×5 window size design used 60% of slices on XC3S200, and 11%
on XC4VSX25. This IP design may be used as a hardware accelerator in a fast image processing SOC.
The main objective of the variable bit rate (VBR) control for a video encoder is to maintain the picture quality during compression. Our constrained VBR control algorithm uses an external output buffer level to feedback the encoder. This algorithm predicts the next buffer level based on the current buffer level and the weighted average picture size of different picture types. The buffer level is fed back to the encoder and the quantizer scale is adjusted accordingly. If the buffer is near empty, the optimized quantizer scale is used. If the buffer is near full, the quantizer scale is increased aggressively to guarantee that the buffer does not overflow. This VBR encoder algorithm was implemented and compared with the CBR encoder algorithm. Several simulation results show that the VBR encoder provides better and more uniform picture quality than the CBR encoder at the same bit rate. For a desired picture quality, our VBR encoder can achieve more compression. If a network can support the VBR output, our constrained VBR control encoder performs better than the CBR control encoder.
Recently, several commercial DSP processors with VLIW (Very Long Instruction Word) architecture were introduced. The VLIW architectures offer high performance over a wide range of multimedia applications that require parallel processing. In this paper, we implement an efficient 2D median filter for VLIW architecture, particularly for Texas Instrument C62x VLIW architecture. Median filter is widely used for filtering the impulse noise while preserving edges in still images and video. The efficient median filtering requires fast sorting. The sorting algorithms were optimized using software pipelining and loop unrolling to maximize the use of the available functional units while meeting the data dependency constraints. The paper describes and lists the optimized source code for the 3 X 3 median filter using an enhanced selection sort algorithm.
Real-time multimedia communication over PSTN (Public Switched Telephone Network) or wireless channel requires video signals to be encoded at the bit rate well below 64 kbits/second. Most of the current works on such very low bit rate video coding are based on H.261 or H.263 scheme. The H.263 encoding scheme, for example, consists mainly of motion estimation and compensation, discrete cosine transform, and run and variable/fixed length coding. Vector quantization (VQ) is an efficient and alternative scheme for coding at very low bit rate. One such VQ code applied to video coding is interframe hierarchical vector quantization (IHVQ). One problem of IHVQ, and VQ in general, is the computational complexity due to codebook search. A number of techniques have been proposed to reduce the search time which include tree-structured VQ, finite-state VQ, cache VQ, and hashing based codebook reorganization. In this paper, we present an IHVQ code with a hashing based scheme to reorganize the codebook so that codebook search time, and thus encoding time, can be significantly reduced. We applied the algorithm to the same test environment as in H.263 and evaluated coding performance. It turned out that the performance of the proposed scheme is significantly better than that of IHVQ without hashed codebook. Also, the performance of the proposed scheme was comparable to and often better than that of the H.263, due mainly to hashing based reorganized codebook.
This paper presents an efficient technique to compress chain-encoded line drawings. The technique, called the address chain code, constructs a codebook containing vectors of chains which recur frequently in the chain-encoded line drawings. The recurrent vectors are encoded as their corresponding addresses in the codebook preceded by header bits. The encoding procedure and an efficient way to organize and label the vectors, which turns out to be somewhat similar to the generalized chain codes, are described in this paper.
This paper presents a terrain model acquisition algorithm for a mobile robot with finite-range sensors in planar terrains. The finite two- dimensional terrain is populated by a finite number of stationary polygonal obstacles. If the robot can see only partial obstacle edge(s) because of its limited range of visibility, our algorithm guides the robot toward the direction in which the incomplete edge of the obstacle is completed at the end vertex. If the robot can see nothing at all within the current range, it is guided in a spiral-like manner to search the terrain for obstacles. In this paper, we formally describe this algorithm and show how it performs with respect to travel distance and the number of scanning operations for various sensor ranges. Also, some examples are shown.
Chain coding families are a collection of line drawing representation techniques which
use the square grid for sampling and quantization. They include chain codes, generalized
chain codes, and polycurve codes. For optimal selection among these techniques, it is
important to investigate the properties of the chain coding families. In this paper, we
evaluate comparatively precision of chain coding families by applying a stochastic line
drawing model. Experimental results show that polycurve codes improve precision over
chain codes and generalized chain codes.
In order to recognize an arbitrary 3D object, it is often required to extract feature points
and feature lines from its surface model. The feature points and feature lines include peaks,
pits, ridge lines, and valley lines. In this paper, we present an efficient technique for finding the
features from the triangular surface model of an arbitrary 3D object. Given a set of surface
data points, we find, using the local adjustment technique, the triangular patches that best fit
the surface of the object. For the resulting triangle-based surface model, unit normal vectors
and side lengths of the triangular patches are used systematically to locate the feature points
and lines of the surface. We present experimental results on simple objects with feature points
and feature lines.
SC928: FPGA Design of Video and Image Processing Algorithms
Field Programmable Gate Arrays (FPGA) have been increasingly used in high-end applications of video and image processing technology. Design implementation using FPGAs greatly reduces the time to market compared to ASICs or custom ICs, while satisfying the heavy processing requirements that cannot be met by DSP processors. This course provides an in-depth and state-of-the-art coverage on the design and FPGA-based implementation of high-performance video and image processing systems. After presenting current FPGA architectures and design tools, several worked-out design examples will be covered including 2-D filters, object matching, and stabilization of shaky video. Lastly, comparative performance evaluation of FPGA, GPU, and CPU for these examples will be discussed.