ASML’s 300mm scanner-systems are built on the TWINSCAN (XT/NXT) platform and yield high productivity levels for dry as well as immersion litho-scanners. NXT:1980Di immersion scanners yield productivity levels as high as 275wph while maintaining the overlay accuracy. The NXT:1980Di can be equipped with a new leveling mode that results in a significant reduction of the time that is spent on measuring the wafer focus height map. In the new leveling mode the focus height map is measured employing the full width of the level sensor and thereby minimizing the number of leveling scans. In this paper we describe the implementation of the LIL-method in the TWINSCAN platform design. Here, we report on the focus / leveling performance for both test as well as customer product wafers, and present a productivity outlook on the performance gain for a selected set of exposure use-cases.
Adjustment and control of the illumination pupil asymmetry is relevant for wafer alignment and overlay of lithography tools. Pupil asymmetries can cause a tilt in aerial image (Aerial Image Tilt, or AIT). This AIT, combined with a focus offset, leads to a horizontal image shift. Pupil asymmetries can be related to a shift of the entire illumination pupil (geometrical telecentricity) caused by illuminator misalign. Another type of pupil asymmetry is energetic imbalance (quantified by pupil Center of Gravity, COG). The scanner can show pupil variation across the exposure slit.
In general the COG at the edge of the slit is often worse than in the center part of the slit. Recently, ASML has released the NXT:1980Di that is equipped with an enhanced illuminator to improve pupil COG variation across the slit. In this paper we explore the performance of this scanner system and show that the AIT variation across the slit is also reduced significantly.
Historically, the block layers are considered "non critical ", as ones requiring less challenging ground rules.
However, continuous technology-driven scaling has brought these layers to a point, where resolution, tolerance and
aspect ratio issue of block masks now present significant process and material challenges. Some of these challenges will
be discussed in this paper.
In recent bulk technology nodes, the deep well implants require an aspect ratio of up to 5:1 in conventional
resist leading to small process margin for line collapse and/or residue. New integration schemes need to be devised to
alleviate these issues, i.e. scaling down the energy of the implant and the STI deep trench to reduce resist thickness, or
new hard mask solutions with high stopping power to be dry etched.
Underlying topography creates severe substrate reflectivity issues that affect CD, tolerance, profiles and
defectivity. In addition to the CD offset due to the substrate, the implant process induces CD shrinkage and resists profile
degradation that affects the devices. Minimizing these effects is paramount for controlling implant level processes and
meeting overall technology requirements. These "non-critical" layers will require the development of more complex
processes and integration schemes to be able to support the future technology nodes. We will characterize these process
constraints, and propose some process / integration solutions for scaling down from 28nm to 20 nm technology node.
The paper describes a process/design co-optimization effort based on an SRAM design to enable a single exposure
contact process for the 28nm technology half node.
As a start, a change to the wiring concept of the standard SRAM design was implemented. The resulting individual
contact layer elements may seem even more resolution critical to the casual observer. But in reality, the flexibility for
source-mask optimization had been significantly improved. In a second step, wafer targets and mask dimension options
(using various kinds of OPC methods and SRAF strategies) were run through several optimization iterations. This
included interlevel considerations due to stringent overlap requirements. Several promising SRAM design as well as
mask options were identified and experimentally verified to finally converge to an optimum mask and wafer target
layout. Said optimum solution still supports an automated OPC approach using standard EDA tools and off the shelf
In a last step, a 1Mbit electrically testable SRAM was designed and manufactured together with alternative SRAM
designs and process options.
After explaining the changes to the wiring of the SRAM design, the paper discusses in great detail various mask
optimization solutions and their consequences on wafer target and printability. Simulation and experimental results are
compared and the concluding optimized solution is explained. Furthermore, some key lithography and etch process
elements that became the single exposure process enabler are explained in more detail. Finally, the paper will take a look
at electrical results of the 1Mbit electrically testable SRAM as the ultimate proof of concept.
Implant level photolithography processes are becoming more challenging each node due to everdecreasing
CD and resist edge placement requirements, and the technical challenge is exacerbated
by the business need to develop and maintain low-cost processes. Optical Proximity Correction
(OPC) using models created based on data from plain silicon substrate is not able to accommodate
the various real device/design scenarios due to substrate pattern effects. In this paper, we show our
systematic study on substrate effect (RX/STI) on implant level lithography CD printing. We also
explain the CD variation mechanism and validate by simulation using well calibrated physical resist
model. Based on the results, we propose an approach to generate substrate-aware OPC rules to
correct for such substrate effects.
In hyper NA immersion lithography which has over 1.0 numerical aperture (NA) exposure system, reflectivity control
between PR and substrate is key technique to overcome resolution limit. Trilayer resist process, which has two layers of
spin-on hard mask (SOH) composed of silicon and carbon, was introduced and applied to various generation of ArF
lithography from dry to immersion process. However, lack of adhesion between PR (hydrophobic) and Si-SOH
(hydrophilic) can cause pattern collapse problem. Moreover, PR profile was not easily adjusted to optimum shape
because some side reaction may be occurred at the interfacial layer between PR and Si-SOH. Herein, we studied how to
control interfacial side reaction between PR and Si-SOH layer in Trilayer process. We approached three conceptual
items: acidity control to PR, uniformity control of Si-SOH itself, and intermixing control of Si-SOH with PR. First, we
checked PR lifting margin with line and space pattern. Although vertical profile was obtained in contact pattern, it was
useless if line pattern was collapsed. With first screening tests, we made a conclusion that a major factor for side reaction
at interfacial layer was penetration of proton into Si-SOH layer produced exposed region. To solve that problem,
intermixing control of Si-SOH with PR was the best solution. We introduced network structure formation with Si-O-Si
bond by cross-linking catalyst. AFM and contact angle data showed improved surface morphology. We could obtain improved pattern profiles with several PR samples. This result can be optimized to various generations of ArF immersion lithography and further more.
With the aid of ArF immersion lithography, semiconductor device node was extended sub-40nm and numerical aperture
(NA) of litho process was exceeded to unity. In this high NA (over 1.0) lithography, however, it is very hard to control
reflectivity between resist and substrate because of total reflection of light. To overcome this problem, the necessities of
dual bottom antireflective coating (BARC) which have different refractivity became to realize. Trilayer resist process,
which has two layers of spin-on hard mask (SOH) composed of silicon and carbon, was introduced and applied to various
generation of ArF lithography from dry to immersion process. However, Lack of adhesion between photoresist
(hydrophobic) and Si-SOH (hydrophilic) layer can cause pattern collapse problem, especially during process of line and
space pattern. Herein we studied modified trilayer resist process. We introduced Alkyldisilazane(ADS) treatment after Si-
SOH coating in trilayer resist process. Silazane functional groups in ADS react with silanols on the Si-SOH surface and
silanols are converted to alkyl siloxane groups. Alkyl siloxane groups are more hydrophobic than silanols, so they can act
as adhesion promoter during lithography process. And the hydrophobicity was increased when more hydrocarbons were
inserted in ADS. We could improve pattern collapse in trilayer resist process and CD uniformity. This process can be
optimized to various generations of ArF immersion lithography and further more.