Advanced processing methods like multiple patterning necessitate improved intra-layer uniformity and balancing monitoring for overlay and CD. To achieve those requirements without major throughout impact, a new advanced mark for measurement is introduced. Based on an optical measurement, this mark delivers CD and overlay results for a specified layer at once. During the conducted experiments at front-end-of-line (FEOL) process area, a mark selection is done and the measurement capability of this mark design is verified. Gathered results are used to determine lithography to etch biases and intra-wafer signatures for CD and overlay. Furthermore, possible use cases like dose correction recipe creation and process signature monitoring were discussed.
Before each wafer exposure, the photo lithography scanner’s alignment system measures alignment marks to correct for placement errors and wafer deformation. To minimize throughput impact, the number of alignment measurements is limited. Usually, the wafer alignment does not correct for intrafield effects. However, after calibration of lens and reticle heating, residual heating effects remain. A set of wafers is exposed with special reticles containing many alignment marks, enabling intra-field alignment. Reticles with a dense alignment layout have been used, with different defined intra-field bias. In addition, overlay simulations are performed with dedicated higher order intra-field overlay models to compensate for wafer-to-wafer and across-wafer heating.
Overlay control for semiconductor devices is getting tighter in recent years. In the past, we may only concern the whether the overlay are in spec or not. However, the spec we concerned was the same for both X and Y directions. To achieve the tighter spec in the future, we may consider the asymmetry specs for X and Y directions separately for some specific layers, such as CONT layer. For example, if the spec of X direction is tighter than Y direction, we can lose the precision of overlay from Y direction to let overlay from X direction more precise. Theoretically, the common overlay models such as HOPC or iHOPC set X and Y directions independently. To reach the goal of loss overly from one direction to preserve the overlay from the other direction, we consider the full map measurement overlay historical data. From these data, we can analyze the data to find which overlay targets are more important to X direction, and we can set these corresponding targets as the new measurement locations. This is one concept of “asymmetry” since the chosen measurement locations can provide more precisely correction for the overlay of specific direction. On the other hand, we use the in spec ratio (ISR) index for all measurement overlay targets on wafer to replace the traditional mean plus 3 sigma (M3S) index, since we have the budgets of both X and Y directions. The in spec ratio is defined as ratio that the residuals of X and Y directions fill the corresponding budgets, simultaneously. Since our goal is to maximize the ISR, the traditional M3S optimization algorithm can be replaced by ISR optimization with different overlay specs. That is the reason we call “asymmetry overlay correction”.
As the process generation migrate to advanced and smaller dimension or pitch, the mask
and resist 3D effects will impact the lithography focus common window severely because of
both individual depth-of-focus (iDOF) range decrease and center mismatch. Furthermore,
some chemical or thermal factors, such as PEB (Post Exposure Bake) also worsen the usable
depth-of-focus (uDOF) performance. So the mismatch of thru-pitch iDOF center should be
considered as a lithography process integration issue, and more complicated to partition the
3D effects induced by optical or chemical factors.
In order to reduce the impact of 3D effects induced by both optical and chemical issues, and
improve iDOF center mismatch, we would like to propose a mask absorber thickness offset
approach, which is directly to compensate the iDOF center bias by adjusting mask absorber
thickness, for iso, semi-iso or dense characteristics in line, space or via patterns to enlarge
common process window, i.e uDOF, which intends to provide similar application as
Flexwave (ASML trademark).
By the way, since mask absorber thickness offset approach is similar to focus tuning or
change on wafer lithography process, it could be acted as the process tuning method of
photoresist (PR) profile optimization locally, PR scum improvement in specific patterns or to
modulate etching bias to meet process integration request.
For mass production consideration, and available material, current att-PSM blank, quartz,
MoSi with chrome layer as hard-mask in reticle process, will be implemented in this
experiment, i.e. chrome will be kept remaining above partial thru-pitch patterns, and act as the
absorber thickness bias in different patterns. And then, from the best focus offset of thru-pitch
patterns, the iDOF center shifts could be directly corrected and to enlarge uDOF by increasing
the overlap of iDOF. Finally, some negative tone development (NTD) result in line patterns will
be demonstrated as well.
A novel method on advanced node for IBO (Image Based Overlay) data extraction accuracy is demonstrated in this work, and here some special design in triple-AIM (Advanced Imaging Metrology) is able to realize the approach.<p> </p> Since triple AIM design has 3 locations left for patterning layers insertion, a new design with 2 layers locations, location-A (inner) and location-B (middle), are generated by 1st pattering, i.e. once lithography exposure, and the 2 marks grouping are formed on dielectric through lithography and etching process with a predetermined overlay "zero offset" through original mask layout design, as illustrated in Fig. (1).<p> </p> And then, as following top photo resist layer, assumed location-C (outer), lithography patterning process, PR coating, exposure and development complete, full triple-AIM patterns is generated, and 3 sets of overlay data could be obtained, A to B, C to B, C to A. <p> </p>Through re-calculating the overlay raw data of current (2nd patterning layer) to previous (1st patterning layer) layer by averaging [C to B] and [C to A], then theoretically the data extraction of sites would be more accuracy, since the variation of local marks signal, induced by inline process instability, could be minimized through the raw data averaging procedure. <p> </p>Moreover, from raw data [A to B], an extra monitor function for detections of the inline process variation, marks selection and recipe setting optimization could be obtained, since marks in [A] and [BB] locations are both generated in 1st patterning, and with the target "zero". <p> </p>So if the raw data [A to BB] is bigger or smaller than "zero" in some degree, there should be some process issue or marks condition setting error in triple-AIM design.
Most fabrication facilities today use imaging overlay measurement methods, as it has been the industry’s reliable workhorse for decades. In the last few years, third-generation Scatterometry Overlay (SCOL™) or Diffraction Based Overlay (DBO-1) technology was developed, along another DBO technology (DBO-2). This development led to the question of where the DBO technology should be implemented for overlay measurements. Scatterometry has been adopted for high volume production in only few cases, always with imaging as a backup, but scatterometry overlay is considered by many as the technology of the future. In this paper we compare imaging overlay and DBO technologies by means of measurements and simulations. We outline issues and sensitivities for both technologies, providing guidelines for the best implementation of each. For several of the presented cases, data from two different DBO technologies are compared as well, the first with Pupil data access (DBO-1) and the other without pupil data access (DBO-2). Key indicators of overlay measurement quality include: layer coverage, accuracy, TMU, process robustness and robustness to process changes. Measurement data from real cases across the industry are compared and the conclusions are also backed by simulations. Accuracy is benchmarked with reference OVL, and self-consistency, showing good results for Imaging and DBO-1 technology. Process sensitivity and metrology robustness are mostly simulated with MTD (Metrology Target Designer) comparing the same process variations for both technologies. The experimental data presented in this study was done on ten advanced node layers and three production node layers, for all phases of the IC fabrication process (FEOL, MEOL and BEOL). The metrology tool used for most of the study is KLA-Tencor’s Archer 500LCM system (scatterometry-based and imaging-based measurement technologies on the same tool) another type of tool is used for DBO-2 measurements. <p> </p>Finally, we conclude that both imaging overlay technology and DBO-1 technology are fully successful and have a valid roadmap for the next few design nodes, with some use cases better suited for one or the other measurement technologies. Having both imaging and DBO technology options available in parallel, allows Overlay Engineers a mix and match overlay measurement strategy, providing back up when encountering difficulties with one of the technologies and benefiting from the best of both technologies for every use case.
The performance of overlay metrology as total measurement uncertainty, design rule compatibility, device correlation, and measurement accuracy has been challenged at the 2× nm node and below. The process impact on overlay metrology is becoming critical, and techniques to improve measurement accuracy become increasingly important. We present a methodology for improving the overlay accuracy. A propriety quality metric, Qmerit, is used to identify overlay metrology measurement settings with the least process impacts and reliable accuracies. Using the quality metric, a calibration method, Archer self-calibration, is then used to remove the inaccuracies. Accuracy validation can be achieved by correlation to reference overlay data from another independent metrology source such as critical dimension–scanning electron microscopy data collected on a device correlated metrology hybrid target or by electrical testing. Additionally, reference metrology can also be used to verify which measurement conditions are the most accurate. We provide an example of such a case.
One of the main issues with accuracy is the bias between the overlay (OVL) target and actual device OVL. In this study, we introduce the concept of device-correlated metrology (DCM), which is a systematic approach to quantify and overcome the bias between target-based OVL results and device OVL values. In order to systematically quantify the bias components between target and device, we introduce a new hybrid target integrating an optical OVL target with a device mimicking critical dimension scanning electron microscope (CD-SEM) target. The hybrid OVL target is designed to accurately represent the process influence on the actual device. In the general case, the CD-SEM can measure the bias between the target and device on the same layer after etch inspection (AEI) for all layers, the OVL between layers at AEI for most cases and after develop inspection for limited cases such as double-patterning layers. The results have shown that for the innovative process compatible hybrid targets the bias between the target and device is small, within the order of CD-SEM noise. Direct OVL measurements by CD-SEM show excellent correlation between CD-SEM and optical OVL measurements at certain conditions. This correlation helps verify the accuracy of the optical measurement results and is applicable for the imaging base OVL method using several target types advance imaging metrology, advance imaging metrology in die OVL, and the scatterometrybase OVL method. Future plans include broadening the hybrid target design to better mimic each layer process conditions such as pattern density. Additionally, for memory devices we are developing hybrid targets which enable other methods of accuracy verification.
Overlay metrology performance as Total Measurement Uncertainty (TMU), design rule compatibility, device correlation and measurement accuracy are been challenged at 2x nm node and below. Process impact on overlay metrology becoming critical, and techniques to improve measurement accuracy becomes increasingly important. In this paper, we present an innovative methodology for improving overlay accuracy. A propriety quality metric, Qmerit, is used to identify overlay metrology measurement settings with least process impacts and reliable accuracies. Using the quality metric, an innovative calibration method, ASC (Archer Self Calibration) is then used to remove the inaccuracies. Accuracy validation can be achieved by correlation to reference overlay data from another independent metrology source such as CDSEM data collected on DCM (Device Correlated Metrology) hybrid target or electrical testing. Additionally, reference metrology can also be used to verify which measurement conditions are the most accurate. In this paper we bring an example of such use case.
As overlay margins shrink for advanced process nodes, a key overlay metrology challenge is finding the measurement conditions which optimize the yield for every device and layer. Ideally, this setup should be found in-line during the lithography measurements step. Moreover, the overlay measurement must have excellent correlation to the device electrical behavior. This requirement makes the measurement conditions selection even more challenging since it requires information about the response of both the metrology target and device to different process variations. In this work a comprehensive solution for overlay metrology accuracy, used by UMC, is described. This solution ranks the different measurement setups by their accuracy, using Qmerit, as reported by the Archer 500. This ranking was verified to match device overlay using electrical tests. Moreover, the use of Archer Self Calibration (ASC) allows further improvement of overlay measurement accuracy.
One of the main issues with overlay error metrology accuracy is the bias between results based on overlay (<strong>OVL</strong>) targets and actual device overlay error. In this study, we introduce the concept of <strong>Device Correlated Metrology</strong> (<strong>DCM</strong>), which is a systematic approach to quantifying and overcoming the bias between target-based overlay results and device overlay issues. For systematically quantifying the bias components between target and device, we introduce a new hybrid target integrating an optical <strong>OVL</strong> target with a device mimicking <strong>CD-SEM</strong> (Critical Dimension – Scanning Electron Microscope) target. The hybrid <strong>OVL</strong> target is designed to accurately represent the process influence found on the real device. In the general case, the <strong>CD-SEM</strong> can measure the bias between target and device on the same layer at AEI (After Etch Inspection) for all layers, the OVL between layers at AEI for most cases and at ADI (After Develop Inspection) for limited cases such as DPL (Double Patterning Lithography). The results shown demonstrate that for the new process compatible hybrid targets the bias between target and device is small, of the order of <strong>CD-SEM</strong> measurement uncertainty. Direct <strong>OVL</strong> measurements by <strong>CD-SEM</strong> show excellent correlation with optical <strong>OVL</strong> measurements in certain conditions. This correlation helps verify the accuracy of the optical measurement results and is applicable for imaging based <strong>OVL</strong> metrology methods using <strong>AIM</strong> or <strong>AIMid OVL</strong> targets, and scatterometry-based overlay methods such as SCOL (Scatterometry <strong>OVL</strong>). Future plans include broadening the hybrid target design to better mimic each layer’s process conditions such as pattern density. We are also designing hybrid targets for memory devices.
Overlay continues to be one of the key challenges for lithography in semiconductor manufacturing, especially in
light of the accelerated pace of device node shrinks. This reality will be especially evident at 20nm node where
DPL and multi-layer overlay will require 4nm or less in overlay control across many critical layers in order to
meet device yield entitlements. The motivation for this paper is based on improving DPL overlay control in face
of the high complexity involved with multi-layer overlay requirements. For example, the DPL-2nd-litho layer
will need to achieve tight registration with the DPL-1st-litho layer, and at the same time, it will need to achieve
tight overlay to the reference-litho layer, which in some cases can also be a DPL layer. Of course, multi-level
overlay measurements are not new, but the combination of increased complexity of multi-DPL layers and
extremely challenging overlay specifications for 20nm node together will necessitate a better understanding of
multi-level overlay control, specifically in terms of root cause analysis of multi-layer related overlay errors and
appropriate techniques for improvement
In this paper, we start with the identification of specific overlay errors caused by multi-layer DPL processing on
full film stack product wafers. After validation of these findings with inter-lot and intra-lot controlled
experiments, we investigate different advanced control techniques to determine how to optimize overlay control
and minimize both intra-lot and inter-lot sources of error. A new approach to overlay data analysis will also be
introduced that combines empirical data with target image quality data to more accurately determine and better
explain the root cause error mechanism as well as provide effective strategies for improved overlay control.
In recent years, layer-to-layer overlay methods moved from the linear regime into non-linear high-order methods in order
to meet the shrinking overlay requirements. In this study we investigate a large number of metrology structures in the
overlapped scribe-line between adjacent scanner fields and the opportunity for improved overlay performance. Sampling
and modeling considerations are discussed. In this investigation we consider the opportunities for high-order stitching
analysis in process control and scanner monitoring. The goal of this work is to establish a systematic methodology for
high order stitching to characterize and reduce overlay errors for advanced IC manufacturing.