Given the continually decreasing k1 factor and process latitude in advanced technology nodes, it is important to fully
understand and control the variables that impact imaging behavior in the lithography process. In this joint work between
TSMC and ASML, we use model-based simulations to characterize and predict the imaging effects of these variables
and to fine-tune the scanner settings based on such information in order to achieve optimal printing results on a perreticle
basis. The scanner modeling makes use of detailed scanner characteristics as well as wafer CD measurements for
accurate model construction. Simulations based on the calibrated model are subsequently used to predict the wafer
impact of changes in tunable scanner parameters for all critical patterns in the product. The critical patterns can be
identified beforehand, either experimentally on wafer, mask or through model simulations. A set of optimized scanner
setting offsets, known as a "scanner tuning recipe" is generated to improve the imaging behavior for the critical patterns.
We have demonstrated the efficacy of this methodology for multiple-use cases with selected ASML scanners and TSMC
processes and will share the achieved improvements on defect reduction and yield improvements.
The increasing complexity of Resolution Enhancements Techniques (RET) in optical lithography requires careful qualification of new reticle designs when they arrive at the wafer fab before commiting them to printing product. In order to qualify the reticle designs at the wafer level, process window qualification (PWQ) is performed by inspecting wafers printed with the reticles to be qualified. The output from the wafer inspection tool provides information on the regions of marginality within the reticle field or features within the die which can have a smaller than expected process window. tsmc Fab 6, an advanced high volume production foundry fab, uses an effective and efficient standardized PWQ procedure to qualify new incoming reticle designs described herein.
There are practical challenges associated with manufacturing implementation of optical photolithography at aggressive design rules. As k1 factors decrease, lithographic focus-exposure process windows have collapsed from a comfortable several-micron depth of focus (DOF) at the 1um technology node, to a challenging to 0.3-to-0.4um at the 0.13um node. As a consequence, the monitoring, management, and control of lithography tool process windows are increasingly important to efficient semiconductor manufacturing. A standard method to deduce lithography-tool process window position and size is based on data from a focus-exposure matrix (FEM) wafer. Unfortunately, the data transfer, analysis, and fab-wide reporting of best focus and other important tool parameters can require a large amount of engineering time and effort, effectively making it impossible in a large-scale production-fab environment. In this work, we present results obtained with a new automated CD-SEM system used to monitor the 0.15um and 0.13um tools and processes in TSMC Fab 6 (70k wafer starts per month). To enable daily FEM-based tool monitoring in this high-volume production fab, these systems provide full “hands-off” automation of data analysis and web-based reporting of best focus, best energy, DOF, image tilt and other significant performance parameters and metrics for each cell. Using these systems, we demonstrate detection of fluctuations in single-tool best focus as small as approximately 20nm using an FEM with focus steps of 200nm. This capability is then used to detect and diagnose process window drifts in single exposure tools as well as mismatches in best focus between multiple exposure tools of several hundred nanometers. The monitoring and reduction of these lithography process window variations have allowed us to increase the performance and efficiency of our advanced lithography manufacturing lines.