In the process of optical proximity correction, layout edge or fragment is migrating to proper position in order
to minimize edge placement error (EPE). During this fragment migration, several factors other than EPE can be also
taken into account as a part of cost function for optimal fragment displacement. Several factors are devised in favor of
OPC stability, which can accommodate room for high mask error enhancement factor (MEEF), lack of process window,
catastrophic pattern failure such as pinch/bridge and improper fragmentation. As technology node becomes finer, there
happens conflict between OPC accuracy and stability. Especially for metal layers, OPC has focused on the stability by
loss of accurate OPC results. On this purpose, several techniques have been introduced, which are target smoothing,
process window aware OPC, model-based retargeting and adaptive OPC. By utilizing those techniques, OPC enables
more stabilized patterning, instead of realizing design target exactly on wafer.
Inevitably, post-OPC layouts become more complicated because those techniques invoke additional edge, or
fragments prior to correction or during OPC iteration. As a result, jogs of post OPC layer can be dramatically increased,
which results in huge number of shot count after data fracturing. In other words, there is trade-off relationship between
data complexity and various methods for OPC stability.
In this paper, those relationships have been investigated with respect to several technology nodes. The mask
shot count reduction is achieved by reducing the number of jogs with which EPE difference are within pre-specified
value. The effect of jog smoothing on OPC output - in view of OPC performance and mask data preparation - was
studied quantitatively for respective technology nodes.
In the past several years, DFM (design for manufacturability) is widely used in semiconductor process. DFM is
to make layout design optimized for manufacturability's sake. Lithography friendly design (LFD) is one branch of DFM.
To enhance process margin of photolithography, layout designers typically modify their layout design with the
application of DFM or LFD tools. Despites those application, it is still not enough to realize enough process window as
technology node goes to beyond 45nm. For these reasons, OPC (Optical proximity correction) engineers apply
additional layout treatment prior to applying OPC. That is called as table-driven retarget, which is typically conducted by
rule-based table. Similar to rule-based OPC, table-driven retarget also has limitations in its application.
In this paper, we presented a model-based retargeting method to overcome the limitation of table-driven retarget.
Once the criteria of process window has been set, we let OPC tool simulate the process window of each layout of design
firstly. Then, if the output value of the simulated result cannot meet the preset criteria, OPC tool resizes the layout
dimension automatically. OPC tool will do retarget-OPC-retarget iterations until process windows of all of designs
become within the criteria. After all, the model-based retarget can guarantee accurate retarget and avoid over or under
retarget in order to improve process window of full chip design.
Rule-based fragmentation has been used for many years in Optical Proximity
Correction (OPC). It breaks the edge of polygons into small pieces according to the
pre-defined rule based on the topography and context before model-based OPC.
Although it works well in most case, it can not place the fragment point onto the
proper position which decided by inherent Optical and process requirement
In this paper, an adaptive fragmentation is proposed. The polygon is first dissected
according to the traditional rule. In the following iteration, the edge is re-fragmented,
in which some fragments are deleted and some new fragments are created, according
to their image properties. Using this method, the dissection point can be placed in the
right position. It can improve the correction accuracy and eliminate the unwanted
fragment at the same time.
Various resolution enhancement techniques have been proposed in order to enable optical lithography
at low k1 imaging, e.g. alt-PSM (phase shift mask), chromeless phase lithography (CPL), double
exposure technique (DET) and double dipole lithography (DDL). In spite of its low throughput in
production, DDL technique is a very attractive solution for low k1 process because of the relatively low
cost of binary or attenuated phase shift masks, which can be combined with strong dipole illuminations
and flexible SRAF rule to enhance the process window. Another attraction of DDL is that dry scanner
still can be used for 45nm node instead of expensive immersion lithography process.
In this paper, two aspects for DDL application have been focused on. The first one is OPC optimization
method for DDL, which includes SRAF optimization, mask decomposition and pixel-based OPC. The
whole flow is optimized specifically for DDL to achieve satisfactory pattern results on wafer. The
second is the overlay issue. Since two DDL masks are exposed in turn, the overlay variation between
two masks becomes dominant factor deteriorating pattern quality. The effect of overlay tolerance is also
studied through process window simulation.
DDL has been demonstrated to be capable of 45nm node logic with dry scanner. The pattern fidelity and
process window of 45nm node SRAM & Random Logic are evaluated for active/gate layer and dark
field metal layer.