Benefiting from motion blur free, Global shutter pixel is very widely used in the design of CMOS image sensors for high speed applications such as motion vision, scientifically inspection, etc. In global shutter sensors, all pixel signal information needs to be stored in the pixel first and then waiting for readout. For higher frame rate, we need very fast operation of the pixel array. There are basically two ways for the in pixel signal storage, one is in charge domain, such as the one shown in , this needs complicated process during the pixel fabrication. The other one is in voltage domain, one example is the one in , this pixel is based on the 4T PPD technology and normally the driving of the high capacitive transfer gate limits the speed of the array operation. In this paper we report a new 9T global shutter pixel based on 3-T partially pinned photodiode (PPPD) technology. It incorporates three in-pixel storage capacitors allowing for correlated double sampling (CDS) and pipeline operation of the array (pixel exposure during the readout of the array). Only two control pulses are needed for all the pixels at the end of exposure which allows high speed exposure control.
In this paper we present a 4 Megapixel high dynamic range, low dark noise and dark current CMOS image sensor, which
is ideal for high-end scientific and surveillance applications. The pixel design is based on a 4-T PPD structure. During
the readout of the pixel array, signals are first amplified, and then feed to a low- power column-parallel ADC array
which is already presented in . Measurement results show that the sensor achieves a dynamic range of 96dB, a dark
noise of 1.47e- at 24fps speed. The dark current is 0.15e-/pixel/s at -20oC.
At present, single-slope analog-to-digital convertor (ADC) is widely used in the readout circuits of CMOS image sensor
(CIS) while its main drawback is the high demand for the system clock frequency. The more pixels and higher ADC
resolution the image sensor system needs, the higher system clock frequency is required. To overcome this problem in
high dynamic range CIS system, this paper presents a 12-bit 500-KS/s cyclic ADC, in which the system clock frequency
is 5MHz. Therefore, comparing with the system frequency of 2<sup>N</sup>×f<sub>S</sub> for the single-slope ADC, where f<sub>S</sub>, N is the
sampling frequency and resolution, respectively, the higher ADC resolution doesn’t need the higher system clock
frequency. With 0.18μm CMOS process, the circuit layout is realized and occupies an area of 8μm×374μm. Post
simulation results show that Signal-to-Noise-and-Distortion-Ratio (SNDR) and Efficient Number of Bit (ENOB) reaches
63.7dB and 10.3bit, respectively.
A two stage 14bit pipeline-SAR analog-to-digital converter includes a 5.5bit zero-crossing MDAC and a 9bit
asynchronous SAR ADC for image sensor readout circuits built in 0.18um CMOS process is described with low
power dissipation as well as small chip area. In this design, we employ comparators instead of high gain and high
bandwidth amplifier, which consumes as low as 20mW of power to achieve the sampling rate of 40MSps and 14bit