Dr. Chi-Min Yuan
Senior staff at NXP Semiconductors
SPIE Involvement:
Conference Chair | Conference Co-Chair | Conference Program Committee | Editor | Author | Instructor
Area of Expertise:
design for manufacturing , optical proximity correction , photomask research and development , lithography process and modeling , mask preparation , photomask marketing and sales
Publications (22)

Proceedings Article | 28 March 2014
Proc. SPIE. 9053, Design-Process-Technology Co-optimization for Manufacturability VIII
KEYWORDS: Semiconductors, Oxides, Metals, Copper, Reliability, Capacitance, Transistors, Optical proximity correction, System on a chip, Temperature metrology

Proceedings Article | 15 March 2012
Proc. SPIE. 8327, Design for Manufacturability through Design-Process Integration VI
KEYWORDS: Lithography, Logic, Clocks, Metals, Ions, Design for manufacturing, Transistors, Analog electronics, Neodymium, Digital electronics

Proceedings Article | 3 April 2010
Proc. SPIE. 7641, Design for Manufacturability through Design-Process Integration IV
KEYWORDS: Optical lithography, Switching, Metals, Particles, Resistance, Printing, Design for manufacturing, Photomasks, Semiconducting wafers, Yield improvement

Showing 5 of 22 publications
Conference Committee Involvement (9)
Design-Process-Technology Co-optimization for Manufacturability XIV
23 February 2020 | San Jose, California, United States
Design-Process-Technology Co-optimization for Manufacturability XIII
27 February 2019 | San Jose, California, United States
Design-Process-Technology Co-optimization for Manufacturability XII
28 February 2018 | San Jose, California, United States
Design-Process-Technology Co-optimization for Manufacturability XI
1 March 2017 | San Jose, California, United States
Design-Process-Technology Co-optimization for Manufacturability X
24 February 2016 | San Jose, California, United States
Showing 5 of 9 Conference Committees
Course Instructor
SC1030: Interaction of Physical Design and Lithography
This course provides attendees with a basic knowledge of physical design and its interaction with lithography. Physical design covers a sequence of steps from logic synthesis, power planning, clock tree synthesis, placement, routing, timing closure, cell library creation and technology library creation. How each step is done has an impact on circuit layout and lithographic patterning. This is especially true when multiple patterning technology began to be adopted at 20nm and below. Based on the feedback of course attendees from previous years, we restrict the primary scope of physical design to four key topics- standard cells, placement, routing and timing closure, that are most relevant to lithographers. In this course, we will devote approximately 2/3 of the time to introducing the concept of physical design, and 1/3 of the time on its interaction with lithography. Also, the instructor will try to cover the physical design aspects relevant to the DPTCO papers to be presented in the conference later in the week.
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