Fully depleted silicon on insulator (FDSOI) circuits provides unique advantages of being of low power, or high performance, or a combination of both if properly deployed. The tradeoff is that designers need to take steps to ensure interference between circuit blocks of different voltage domains, and antenna damages do not occur. This paper describes an efficient design, which combines guard rings and antenna diodes into one, to resolve these potential issues.
To date, majority of the papers presented in the conference focused on how to print smaller transistors that run faster. In a different market such as safety-focused automotive market, “smaller and faster” are replaced by “tougher and living longer”. In such a market, a chip has to endure a wide range of operating temperature from -40C to 150C, and is required to have an extremely low field failure rate over 10+ years. There is a wide range of design techniques that can be deployed to improve the quality of a chip. In this paper, we present some of these design techniques that are related to the physical aspects of standard cells.
In the SPIE Microlithography DFM conference, the number of papers related to physical design has been steadily increasing in the last few years. Since the majority of the audience in this conference has a background in lithography, some of the physical design-related terminologies and methods described in the presentation may be hard to understand. This paper gives a basic introduction to the physical design that is applicable to lithographers. The goal of the paper is not to enable a lithographer to begin working as a physical designer. Instead, it is to help lithographers understand some of the basics of physical design, so that they can better comprehend other DFM papers presented at the conference.
Layout sizing in the mask preparation step is commonly used on critical layers to improve printing process windows.
The current flow of yield calculation based on critical areas of a layout typically does not take into account this sizing
step. In this paper, we propose a new and simple flow that accounts for the sizing to improve the accuracy of yield
calculation. We compare the calculated results using the current and sizing-aware flow to demonstrate the differences.
We also show that results from the sizing-aware flow better match the calculated circuit switching power, which already takes into account this sizing step.
Chemical Mechanical Polishing (CMP) has been used in the manufacturing process for copper (Cu) damascene process.
It is well known that dishing and erosion occur during CMP process, and they strongly depend on metal density and line
width. The inherent thickness and topography variations become an increasing concern for today's designs running
through advanced process nodes (sub 65nm). Excessive thickness and topography variations can have major impacts on
chip yield and performance; as such they need to be accounted for during the design stage.
In this paper, we will demonstrate an accurate physics based CMP model and its application for CMP-related hotspot
detection. Model based checking capability is most useful to identify highly environment sensitive layouts that are prone
to early process window limitation and hence failure. Model based checking as opposed to rule based checking can
identify more accurately the weak points in a design and enable designers to provide improved layout for the areas with
highest leverage for manufacturability improvement. Further, CMP modeling has the ability to provide information on
interlevel effects such as copper puddling from underlying topography that cannot be captured in Design-for-
Manufacturing (DfM) recommended rules.
The model has been calibrated against the silicon produced with the 45nm process from Common Platform (IBMChartered-
Samsung) technology. It is one of the earliest 45nm CMP models available today. We will show that the
CMP-related hotspots can often occur around the spaces between analog macros and digital blocks in the SoC designs.
With the help of the CMP model-based prediction, the design, the dummy fill or the placement of the blocks can be
modified to improve planarity and eliminate CMP-related hotspots. The CMP model can be used to pass design
recommendations to designers to improve chip yield and performance.
In recent years, various DFM techniques are developed and adopted by the designers to improve circuit yield and
reliability. The benefits from applying a DFM technique to a circuit often come at the expense of degrading other
process or design attributes. In this paper, we discuss two widely deployed techniques: double vias and wire
spreading/widening, show the benefits and trade-offs of their usage, and practical ways to implement them in SoC
To provide fabless designers the same advantage as Integrated Device Manufacturer (IDMs), a design-oriented litho
model has been calibrated and an automated lithography (litho) hotspot detection and fixing flow has been implemented
during final routing optimization.
This paper shows how a design-oriented litho model was built and used to automate a litho hotspot fixing design flow.
The model, calibrated and validated against post-OPC contour data at 99%, was embedded into a Litho Physical
Analyzer (LPA) tech file. It allowed the litho contour of drawn layouts to be simulated at full chip level to detect litho
hotspots and to provide fixing guidelines. Automated hotspots fixing was hence made possible by feeding the guidelines
to the fixing tools in an industry based integrated flow. Post-fixing incremental checks were also performed to converge
to a clean design.
This paper describes a simple technique to improve the process latitude for contact and via printing. The technique
applies a selective upsizing algorithm to the mask data during the mask preparation step. For each contact or via, the
algorithm looks for available spaces by checking relevant layers near it. When spaces are available, selective edges of a
contact or via will be sized to improve the process latitude. This paper describes algorithms used to implement this
technique. Multiple designs of various design styles are used to demonstrate the effectiveness of the algorithms. The
implications on mask preparation, mask making and wafer processing are also discussed.
In order to achieve the necessary OPC model accuracy, the requisite number of SEM CD measurements has
exploded with each technology generation. At 65 nm and below, the need for OPC and/or manufacturing
verification models for several process conditions (focus, exposure) further multiplies the number of
measurements required. SEM-contour based OPC model calibration has arisen as a powerful approach to
deliver robust and accurate OPC models since every pixel now adds information for input into the model,
substantially increasing the parameter space coverage. To date however, SEM contours have been used to
supplement the hundreds or thousands of discreet CD measurements to deliver robust and accurate models.
While this is still perhaps the optimum path for high accuracy, there are some cases where OPC test
patterns are not available, and the use of existing circuit patterns is desirable to create an OPC model.
In this work, SEM contours of in-circuit patterns are utilized as the sole data source for OPC model
calibration. The use scenario involves 130 nm technology which was initially qualified for production with
the use of rule-based OPC, but is shown to benefit from model based OPC. In such a case, sub-nanometer
accuracy is not required, and in-circuit features can enable rapid development of sufficiently accurate
models to provide improved process margin in manufacturing.
GDSII file size is not very well correlated with the computer runtime and memory required to perform RET processing. Occasionally, small files can take many hours to process, while large files can run very quickly. The ability to accurately predict resource requirements for RET processing is essential to optimizing RET automation. In this paper, we examine GDSII complexity metrics in an effort to find a method for predicting RET processing resource requirements.
The cost of developing and deploying optical proximity correction (OPC) technology has become a non-negligible part of the total lithography cost of ownership (CoO). In this paper, we present our efforts to reduce costs associated with OPC in the development phase for the 90nm node, and production phase for the 130nm node.
The patterning of logic layouts for the 65nm and subsequent device generations will require the implementation of new capabilities in process control, optical proximity correction (OPC), resolution enhancement technique (RET) complexity, and lithography-design interactions. Many of the methods used to implement and verify these complex interactions can be described as design for manufacturability (DFM) techniques. In this paper we review a wide range of existing non-lithographic and lithographic DFM techniques in the semiconductor industry. We also analyze existing product designs for DFM technique implementation potential and propose new design methods for improving lithographic capability.
The 65nm device generation will require steady improvements in lithography scanners, resists, reticles and OPC technology. 193nm high NA scanners and illumination can provide the desired dense feature resolution, but achieving the stringent overall 65nm logic product requirements necessitates a more coherent strategy of reticle, process, OPC, and design methods than was required for previous generations. This required integrated patterning solution strategy will have a fundamental impact on the relationship between design and process functions at the 65nm device node.
Due to the challenging design rule and CD control requirements of the 100 nm device generation, a large number of complex patterning techniques are likely to be used for random logic devices. The complexity of these techniques places considerable strain upon model-based OPC software to identify and compensate for a wide range of printing non- idealities. Additionally, the rapidly increasing cost of advanced reticles has increased the urgency of obtaining reticles devoid of process limiting design or OPC errors. We have evaluated the capability of leading edge model-based OPC software to meet the challenging lithography needs of the 100 nm device generation. Specifically, we have implemented and verified model usefulness to correct for pattern deformation in complex binary gate, contact and via processes utilizing highly optimized illumination. Additionally, we present results showing the abilities of model-based methods to accurately find design related printing problems in complementary phase shift gate designs before they are committed to an expensive reticle.
A new workstation-based rigorous 3D model for simulation of light scattering by alignment structures is introduced. The model extends a successful 2D lithography model, and has been applied to the simulation of periodic 3D alignment marks on a resist covered silicon substrate. The theory behind the new model is presented, and examples are given of the model's results and computational efficiency.
The manufacture of an embedded attenuating phase shift mask (E-APSM) is the simplest among all the phase shift mask (PSM) types. This is because an E-APSM provides the necessary attenuation and phase shift requirements using a single layer absorber film. Therefore, the tasks of patterning, inspection and repair are much easier to accomplish than for a multi-level quartz etched or SOG/SiO2 coated PSM. Reports in literature indicate that an E-APSM, also referred to as a single-layer half-tone PSM, is likely to be used for the contact masking layer in the manufacture of 64 M-bit DRAMs. It has also been stated that defect-free E-APSMs will be manufactured using currently available mask making tools. Therefore, it could be inferred that the defect specifications for an E-APSM are expected to be the same as that for a standard chrome mask. Perturbation modeling studies indicate that this should be true. An experimental study of repair and printability of defects on contacts on an E- APSM, using a chrome-based embedded attenuating film was performed. Exposures were made on an i-line stepper with NA equals 0.6 and sigma equals 0.6. Oxide wafers were coated with a high contrast i-line resist and the contact pattern was transferred into the oxide using a decorative etch process. Measurements were made using a SEM. The wafer results were also compared with printability studies done using an aerial imaging measurement system. The results of repairs done on 1 micrometer size defects on 2 micrometer size contacts indicate that the currently available laser repair tool was successful in restoring the lithographic performance of the E-APSM contacts to an acceptable level.
In this work we demonstrate the power, speed, and effectiveness of an automated rules-based approach for performing optical proximity correction. The approach applies to both conventional and phase-shifting mask layouts for optical lithography. Complex imaging, substrate, and process phenomena can be folded into comparatively few rules parameters. Using simple arithmetic, these parameters pre-compensate the layout for the combined proximity effects. The rules consist of edge rules and corner rules for biasing feature edges and for adding sub-resolution assist features. This paper describes an integrated solution that includes rules parameter generation and fast, hierarchical rules application. Experimental results demonstrate improved edge placements and wider process latitude than for non- corrected layouts.
The creation of stable, defect free, and correctly biased phase shifting masks (PSMs) is a difficult task. The behavior of PSMs, with their complicated structures and topographies, is highly sensitive to process parameters. A method of equalizing the intensity transmission by applying a wet etchant to the reticle and etching back both shifted and unshifted openings has been proposed. The etchback is used to reduce or alter the sidewall light scattering effects, leading to intensity equalization. The proposed method has been shown to cause intensity equalization for i-line and DUV illuminated alternating PSMs. However, many questions remain about the effective use of this method.
Numerical algorithms employing the ID imaging model and the 2D wave-guide scattering model were implemented to achieve high speed in simulating high NA i-line processes. The CPU consumption and the range of validity of the models used were discussed. The simulator was applied to study the possibility of imaging 0.35/mi lines and spaces(L/S) utilizing lenses of NA=0.55, 0.60 and 0.65 and single layer resist (SLR) processes.
A new vector (true two-dimensional) optical lithography modeling program, METROPOLE, is presented which incorporates arbitrary mask geometries. This rigorous model is thus ideally suited for the simulation of phase shifting masks. The efficiency of the electric field calculations, both within the mask and on the substrate structures, allows its use on accessible engineering workstations. Several simulation examples are presented, and include the new phase shifting on the substrate technique (POST).
The aim ofour work was to develop rigorous models to study various optical alignment and metrology schemes implemented in commercial tools. These schemes indude wafer alignment schemes in steppers and linewidth measurement schemes in optical microscopes. A simulator called METRO based on the models developed has been implemented to facilitate this task. Theoretical and experimental verification efforts have been performed to examine the validity of the simulation results and good agreement has been obtained. By utilizing METRO process engineers can gain more insight into the equipment under operation so as to obtain more accurate alignment and measurement results. Also the equation formulation in METRO is general enough so that optics designers can easily adopt or modify the code to help in devising innovative alignment and metrology schemes. 1.
SC1030: Interaction of Physical Design and Lithography
This course provides attendees with a basic knowledge of physical design and its interaction with lithography. Physical design covers a sequence of steps from logic synthesis, power planning, clock tree synthesis, placement, routing, timing closure, cell library creation and technology library creation. How each step is done has an impact on circuit layout and lithographic patterning. This is especially true when multiple patterning technology began to be adopted at 20nm and below.
Based on the feedback of course attendees from previous years, we restrict the primary scope of physical design to four key topics- standard cells, placement, routing and timing closure, that are most relevant to lithographers. In this course, we will devote approximately 2/3 of the time to introducing the concept of physical design, and 1/3 of the time on its interaction with lithography. Also, the instructor will try to cover the physical design aspects relevant to the DPTCO papers to be presented in the conference later in the week.