The design of integrated circuits (ICs) has been made possible by a simple contract between design and manufacturing: Manufacturing teams encapsulated their process capabilities into a set of design rules such as minimum width and spacing or overlap for each layer, and designers complied with these design rules to get a manufacturable IC. However, since the advent of 130nm technology, designers have to play by the new rules of sub-90nm technologies. The simple design rules have evolved into extremely complex, context-dependent rules. Minimum design rules have been augmented with many levels of yield-driven recommended guidelines. One of the main drivers behind these complex rules is the increase in optical proximity effects that are directly impacting systematic and parametric yields for sub-90nm designs. A design's sensitivity to optical proximity effects increases as features get smaller, however design engineers do not have visibility into the manufacturability of these features.
A genuine design for manufacturing (DFM) solution for designers should provide a fast, easy-to-use and cost-effective solution that accurately predicts the designs sensitivity to shape variations through out the design process. It should identify and reduce design sensitivity by predicting and reducing shape variations. The interface between manufacturing and design must provide designers with the right information to allow them to maximize the manufacturability of their design while shielding them from the effects of resolution enhancement technologies (RET) and manufacturing complexity. This solution should also protect the manufacturing know-how in the case of a fabless foundry flow. Currently, the interface between manufacturing and design solely relies on design rules that do not provide these capabilities.
A common proposition for design engineers in predicting shape variation is to move the entire RET/OPC/ORC into the hands of the designer. However, this approach has several major practicality issues that make it unfeasible, even as a "service" offered to designers:
1- Cost associated with replicating the flow on designer's desktop.
2- The ability of designers to understand RET/OPC and perform lithographic judgments.
3- Confidentiality of the recipes and lithographic settings, especially when working with a foundry.
4- The level of confidence the fab/foundry side has in accepting the resulting RET/OPC.
5- Runtime and data volume explosion.
6- The logistics of reflecting RET/OPC and manufacturing changes.
7- The ability to tie this capability to EDA optimization tools.
In this paper we present a new technique and methodology that overcomes these hurdles and meets both the designer and manufacturing requirements by providing a genuine DFM solution to designers. We outline a new manufacturing-to-design interface that has evolved from rule-based to model-based, and provides the required visibility to the designer on their design manufacturability. This approach is similar to other EDA approaches which have been used to successfully capture complex behavior by using a formulation that has a higher level of abstraction (for example, SPICE for transistor behavior). We will present how this unique approach uses this abstracted model to provide very accurate prediction of shape variations and at the same time, meet the runtime requirements for a smooth integration into the design flow at 90nm and below. This DFM technology enables designers to improve their design manufacturability, which reduces RET complexity, reduces mask cost and time to volume, and increases the process window and yield.
Simulation-based techniques assisted mask and wafer metrology and inspection have become increasingly important with the growth of the sub-wavelength gap in optical photolithography. This paper describes a method for full-chip layout verification based on fast calculation of the mask error enhancement factor (MEEF). Because of the significant amount of MEEF computations necessary for large layouts, we discuss a methodology that takes advantage of distributed computing environment to significantly shorten the total run time. Additionally, MEEF calculations can be selectively reduced to layout locations that meet specific criteria, which allows to not only reduce the overall simulation time, but also to decrease the output data volume transferred to the mask inspection equipment. After MEEF is calculated, a SQL database is used to generate a summary report and to efficiently locate high-MEEF areas, which could be sent in a form marker files to metrology tools.