In this paper, we present a family of large format CIS’s designed for dental x-ray applications. The CIS areas vary from
small 31.5mm x 20.1mm, to medium 34.1mm x 26.3mm, to large 37.1mm x 26.3mm. Pixel size is 19.5um x 19.5um.
The sensor family was fabricated in a 0.18um CIS process. Stitching is used in the CIS fabrication for the medium and
large size sensors. We present the CIS and detector system design that includes pixel circuitry, readout circuitry, x-ray
trigger mechanism, scintillator, and the camera electronics. We also present characterization results including the
detector performances under both visible light and x-ray radiation.
In this paper, we present an overview of high-performance CMOS image sensor products developed at BAE SYSTEMS
Imaging Solutions designed to satisfy the increasingly challenging technical requirements for image sensors used in
advanced scientific, industrial, and low light imaging applications. We discuss the design and present the test results of a
family of image sensors tailored for high imaging performance and capable of delivering sub-electron readout noise,
high dynamic range, low power, high frame rates, and high sensitivity. We briefly review the performance of the
CIS2051, a 5.5-Mpixel image sensor, which represents our first commercial CMOS image sensor product that
demonstrates the potential of our technology, then we present the performance characteristics of the CIS1021, a full HD
format CMOS image sensor capable of delivering sub-electron read noise performance at 50 fps frame rate at full HD
resolution. We also review the performance of the CIS1042, a 4-Mpixel image sensor which offers better than 70% QE
@ 600nm combined with better than 91dB intra scene dynamic range and about 1 e- read noise at 100 fps frame rate at
As bio-technology transitions from research and development to high volume production, dramatic improvements in
image sensor performance will be required to support the throughput and cost requirements of this market. This includes
higher resolution, higher frame rates, higher quantum efficiencies, increased system integration, lower read-noise, and
lower device costs. We present the performance of a recently developed low noise 2048(H) x 2048(V) CMOS image
sensor optimized for scientific applications such as life science imaging, microscopy, as well as industrial inspection
applications. The sensor architecture consists of two identical halves which can be operated independently and the
imaging array consists of 4T pixels with pinned photodiodes on a 6.5μm pitch with integrated micro-lens. The operation
of the sensor is programmable through a SPI interface. The measured peak quantum efficiency of the sensor is 73% at
600nm, and the read noise is about 1.1e- RMS at 100 fps data rate. The sensor features dual gain column parallel ouput
amplifiers with 11-bit single slope ADCs. The full well capacity is greater than 36ke-, the dark current is less than
7pA/cm<sup>2</sup> at 20°C. The sensor achieves an intra-scene linear dynamic range of greater than 91dB (36000:1) at room
In this paper, we present a CMOS digital intra-oral sensor for x-ray radiography. The sensor system consists of a custom
CMOS imager, custom scintillator/fiber optics plate, camera timing and digital control electronics, and direct USB
communication. The CMOS imager contains 1700 x 1346 pixels. The pixel size is 19.5um x 19.5um. The imager was
fabricated with a 0.18um CMOS imaging process. The sensor and CMOS imager design features chamfered corners for
patient comfort. All camera functions were integrated within the sensor housing and a standard USB cable was used to
directly connect the intra-oral sensor to the host computer. The sensor demonstrated wide dynamic range from 5uGy to
1300uGy and high image quality with a SNR of greater than 160 at 400uGy dose. The sensor has a spatial resolution
more than 20 lp/mm.
We present the performance of a CMOS image sensor optimized for next generation fused day/night vision systems.
The device features 5T pixels with pinned photodiodes on a 6.5μm pitch with integrated micro-lens. The 5T pixel
architecture enables both correlated double sampling (CDS) to reduce noise for night time operation, and a lateral antiblooming
drain for day time operation. The measured peak quantum efficiency of the sensor is above 55% at 600nm,
and the median read noise is less than 1e- RMS at room temperature. The sensor features dual gain 11-bit data output
ports and supports 30 fps and 60 fps. The full well capacity is greater than 30ke-, the dark current is less than 3.8pA/cm<sup>2</sup>
at 20ºC, and the MTF at 77 lp/mm is 0.4 at 550nm. The sensor also achieves an intra-scene linear dynamic range of
greater than 90dB (30000:1) for night time operation, and an inter-scene linear dynamic range of greater than 150dB for
complete day/night operability.
In this paper we describe a 5.5Mpixel 100 frames/sec wide-dynamic-range low-noise CMOS image sensor (CIS)
designed for scientific applications. The sensor has 6.5μm pitch 5T pixels with pinned photodiodes and integrated
microlenses. The 5T pixel architecture enables low noise rolling and global shutter operation. The measured peak
quantum efficiency of the sensor is greater than 55% at 550nm, the Nyquist MTF is greater than 0.4 at 550nm, and the
linear full well capacity is greater than 35ke-. The measured rolling and global shutter readout noise are 1.28e- RMS
and 2.54e- RMS respectively at 30 f/s and 20°C. The pinned photodiode dark current is less than 3.8pA/cm<sup>2</sup> at 20°C.
The sensor achieves an intra-scene linear dynamic range in rolling shutter operation of greater than 86dB (20000:1) at
room temperature. In global shutter readout the shutter efficiency is greater than 1000:1 with 500nm illumination.
The field of ultrafast x-ray science is flourishing, driven by emerging synchrotron sources (e.g., time-slice storage rings, energy recovery linacs, free electron lasers) capable of fine time resolution. New hybrid x-ray detectors are under development in order to exploit these new capabilities.
This paper describes the development of a 2160 x 2560 CMOS image sensor (CIS) system with a 6.5 µm pitch optimized for time-resolved x-ray scattering studies. The system is single photon quantum limited from 8 keV to 20 keV. It has a wide dynamic range and can operate at 100 Hz full-frame and at higher frequencies using a region-of-interest (ROI) readout. Fundamental metrics of linearity, dynamic range, spatial resolution, conversion gain, sensitivity and Detective Quantum Efficiency are estimated. Experimental time-resolved data are also presented.
In this paper we present a VNIR solid state sensor technology suitable for next generation fused night vision systems.
This technology is based on a highly optimized low power 0.18um CMOS image sensor (CIS) process. We describe a
320(H) x 240(V) pixel prototype sensor based on this technology. The sensor features 5T pixels with pinned
photodiodes on a 6.5μm pitch with integrated micro-lens. The 5T pixel architecture enables both correlated double
sampling (CDS) and a lateral anti-blooming drain. The measured peak quantum efficiency of the sensor is greater than
50% at 600nm, and the read noise is less than 1e- RMS at room temperature. The sensor does not have any
multiplicative noise. The full well capacity is greater than 40ke-, the dark current is less than 3.8pA/cm2 at 20ºC, and the
MTF at 77 lp/mm is 0.4 at 600nm. The sensor also achieves an intra-scene linear dynamic range of greater than 90dB
(30000:1) at room temperature.
CCDs have been the primary sensor in imaging systems for x-ray diffraction and imaging
applications in recent years. CCDs have met the fundamental requirements of low noise,
high-sensitivity, high dynamic range and spatial resolution necessary for these scientific
applications. State-of-the-art CMOS image sensor (CIS) technology has experienced
dramatic improvements recently and their performance is rivaling or surpassing that of
most CCDs. The advancement of CIS technology is at an ever-accelerating pace and is
driven by the multi-billion dollar consumer market. There are several advantages of CIS
over traditional CCDs and other solid-state imaging devices; they include low power,
high-speed operation, system-on-chip integration and lower manufacturing costs. The
combination of superior imaging performance and system advantages makes CIS a good
candidate for high-sensitivity imaging system development.
This paper will describe a 1344 x 1212 CIS imaging system with a 19.5μm pitch
optimized for x-ray scattering studies at high-energies. Fundamental metrics of linearity,
dynamic range, spatial resolution, conversion gain, sensitivity are estimated. The
Detective Quantum Efficiency (DQE) is also estimated. Representative x-ray diffraction
images are presented. Diffraction images are compared against a CCD-based imaging
We present the design and test results of a prototype 4T CMOS image sensor fabricated in 0.18-μm technology
featuring 20 different 6.5 μm pixel pitch designs. We review the measured data which clearly show the impact of the
pixel topologies on sensor performance parameters such as conversion gain, read noise, dark current, full well capacity,
non-linearity, PRNU, DSNU, image lag, QE and MTF. Read noise of less than 1.5e- rms and peak QE greater than
70%, with microlens, are reported.
In this paper, we present an overview of large area detector arrays and new sensor technologies currently under development at Fairchild Imaging. We discuss on-going development efforts aimed at satisfying the increasing need for large format, scientific grade detectors, and review significant progress in achieving higher spatial resolution in large area back-illuminated CCDs. We also present the performance characteristics of a new prototype CCD/CMOS hybrid sensor designed for low light level imaging and capable of high speed, low power, and very low noise.
A multitude of scientific, medical, and defense applications require imaging at low light level. Examples include:
live-cell fluorescence microscopy, wavefront sensing for adaptive optics, and night vision. To address these
applications low light level sensors need to have low noise, high quantum efficiency, low lag, high MTF, high
frame rates, and low power. Over the past 50 years a variety of techniques have been developed to analyze
and compare these technologies. The purpose of this paper is to develop an analytical method for estimating
limiting resolution of low light level sensors and cameras. We present a communication theory based model
that is designed to enable rapid evaluation of low light level sensors and aid in the understanding of how these
systems operate. This model can be applied to electron multiplied CCDs, electron bombarded CMOS sensors,
and hybrid CCD/CMOS sensors. In addition we also describe a device physics based low light level camera
simulator. We compare our model to the camera simulator and show that the model can be used to accurately
predict camera performance. In addition the computational complexity of our model is 1/150 of a complete low
light level camera simulator.
We present a CCD / CMOS hybrid focal plane array (FPA) for low light level imaging applications. The hybrid approach combines the best of CCD imaging characteristics (e.g. high quantum efficiency, low dark current, excellent uniformity, and low pixel cross talk) with the high speed, low power and ultra-low read noise of CMOS readout technology. The FPA is comprised of two CMOS readout integrated circuits (ROIC) that are bump bonded to a CCD imaging substrate. Each ROIC is an array of Capacitive Transimpedence Amplifiers (CTIA) that connect to the CCD columns via indium bumps. The proposed column parallel readout architecture eliminates the slow speed, high noise, and high power limitations of a conventional CCD. This results in a compact, low power, ultra-sensitive solid-state FPA that can be used in low light level applications such as live-cell microscopy and security cameras at room temperature operation. The prototype FPA has a 1280×1024 format with 12-um square pixels. Measured dark current is less than 5.8 pA/cm<sup>2</sup> at room temperature and the overall read noise is as low as 2.9e at 30 frames/sec.
CMOS image sensors are capable of very high frame rate non- destructive readout. This capability and the potential of integrating memory and signal processing with the sensor on the same chip enable the implementation of many still and video imaging applications. An important example is dynamic range extension, where several images are captured during a normal exposure time - shorter exposure time images capture the brighter areas of the scene while longer exposure time images capture the darker areas of the scene. These images are then combined to form a high dynamic range image. Dynamic range is extended at the high end by detecting saturation, and at the low end using linear estimation algorithms that reduce read noise. With the need to reduce pixel size and integrate more functionality with the sensor, CMOS image sensors need to follow the CMOS technology scaling trend. Well capacity, however, decreases with technology scaling as pixel size and supply voltages are reduced. As a result, SNR decreases potentially to the point where even peak SNR is inadequate. In this paper, we propose a self-reset pixel architecture, which when combined with multiple non-destructive captures can increase peak SNR as well as enhance dynamic range. Under high illumination, self-resetting 'recycles' the well during integration resulting in higher effective well capacity, and thus higher SNR. A recursive photocurrent estimation algorithm that takes into consideration the additional noise due to self- resetting is described. Simulation results demonstrate the SNR increase throughout the enhanced photocurrent range with 10dB increase in peak SNR using 32 captures.
CMOS image sensors have benefitted from technology scaling down to 0.35 micrometers with only minor process modifications. Several studies have predicted that below 0.25 micrometers , it will become difficult, if not impossible to implement CMOS image sensors with acceptable performance without more significant process modifications. To explore the imaging performance of CMOS Image sensors fabricated in standard 0.18 micrometers technology, we designed a set of single pixel photodiode and photogate APS test structures. The test structures include pixels with different size n+/pwell and nwell/psub photodiodes and nMOS photogates. To reduce the leakages due to the in-pixel transistors, the follower, photogate, and transfer devices all use 3.3V thick oxide transistors. The paper reports on the key imaging parameters measured from these test structures including conversion gain, dark current and spectral response. We find that dark current density decreases super-linearly in reverse bias voltage, which suggest that it is desirable to run the photodetectors at low bias voltages. We find that QE is quite low due to high pwell doping concentration. Finally we find that the photogate circuit suffered from high transfer gate off current. QE is not significantly affected by this problem, however.
CMOS image sensors generally suffer form lower dynamic range than CCDs due to their higher readout noise. Their high speed readout capability and the potential of integrating memory and signal processing with the sensor on the same chip, open up many possibilities for enhancing their dynamic range. Earlier work have demonstrated the use of multiple non-destructive samples to enhance dynamic range, while achieving higher SNR than using other dynamic range enhancement schemes. The high dynamic range image is constructed by appropriately scaling each pixel's last sample before saturation. Conventional CDS is used to reduce offset FPN and reset noise. This simple high dynamic range image construction scheme, however, does not take full advantage of the multiple samples. Readout noise power, which doubles as a result of performing CDS, remain as high as in conventional sensor operation. As a result dynamic range is only extended at the high illumination end. The paper explores the use of linear mean-square-error estimation to more fully exploit the multiple pixel samples to reduce readout noise and thus extend dynamic range at the low illumination end. We present three estimation algorithms: (1) a recursive estimator when reset noise and offset FPN are ignored, (2) a non-recursive algorithm when reset noise and FPN are considered, and (3) a recursive estimation algorithm for case (2), which achieves mean square error close to the non-recursive algorithm without the need to store all the samples. The later recursive algorithm is attractive since it requires the storage of only a few pixel values per pixel, which makes its implementation in a single chip digital imaging system feasible.
CMOS image sensor designers take advantage of technology scaling either by reducing pixel size or by adding more transistors to the pixel. In both cases, the distance from the chip surface to the photodiode increases relative to the photodiode planar dimensions. As a result, light must ravel through an increasingly deeper and narrower `tunnel' before it reaches the photodiode. This is especially problematic for light incident at oblique angles; the narrow tunnel walls cast a shadow on the photodiode, which in turn severely reduces its effective QE. We refer to this phenomenon as pixel vignetting. The paper presents experimental results from a 640 X 512 CMOS image sensor fabricated using a 0.35(mu) 4-layer metal CMOs process that shows significant QE reduction of up to 50% for off-axis relative to on-axis pixels. Using simple geometric models of the sensor and the imaging optics, we compare the QE for on and off-axis pixels. We find that our analysis results support the hypothesis that the experimentally observed QE reduction is indeed due to pixel vignetting. We show that pixel vignetting becomes more severe as CMOS technology scales, even for a 2-layer metal APS pixel. Finally, we briefly discuss several potential solutions to the pixel vignetting problem.
Techniques for characterizing CCD imagers have been developed over many years. These techniques have been recently modified and extended to CMOS PPS and APS imagers. With the scaling of CMOS technology, an increasing number of transistors can be added to each pixel. A promising direction to utilize these transistors is to perform pixel level ADC. The authors have designed and prototyped two imagers with pixel level Nyquist rate ADC. The ADCs operate in parallel and output data one bit at a time. The data is read out of the imager array one bit plane at a time in a manner similar to a digital memory. Existing characterization techniques could not be directly used for these imagers, however, since there is no facility to read out the analog pixel values before ADC, and the ADC resolution is limited to only 8 bits. Fortunately, the ADCs are fully testable electrically without the need for any light or optics. This makes it possible obtain the ADC transfer curve, which greatly simplifies characterization. In this paper we describe how we characterize our pixel level ADC imagers. To estimate QE, we measure the imager photon to DN transfer curve and the ADC transfer curve. We find that both curves are quite linear.Using an estimate of the sense node capacitance we then estimate sensitivity, and QE. To estimate FPN we model it as an outcome of the sum of two uncorrelated random processes, one representing the ADC FPN, and the other representing the photodetector FPN, and develop estimators for the model parameters form imager data under uniform illumination. We report characterization result for a 640 by 512 imager, which was fabricated in a 0.35 micrometers standard digital CMOS process.
Fixed pattern noise (FPN) for a CCD sensor is modeled as a sample of a spatial white noise process. This model is, however, not adequate for characterizing FPN in CMOS sensors, since the redout circuitry of CMOS sensors and CCDs are very different. The paper presents a model for CMOS FPN as the sum of two components: a column and a pixel component. Each component is modeled by a first order isotropic autoregressive random process, and each component. Each component is modeled by a first order isotropic autoregressive random process, and each component is assumed to be uncorrelated with the other. The parameters of the processes characterize each component of the FPN and the correlations between neighboring pixels and neighboring columns for a batch of sensor. We show how to estimate the model parameters from a set of measurements, and report estimates for 64 X 64 passive pixel sensor (PPS) and active pixel sensor (APS) test structures implemented in a 0.35 micron CMOS process. High spatial correlations between pixel components were measured for the PPS structures, and between the column components in both PPS and APS. The APS pixel components were uncorrelated.