The NTD (Negative Tone Developer) process has been embraced as a viable alternative to traditionally, more conventional, positive tone develop processes. Advanced technology nodes have necessitated the adopting of NTD processes to achieve such tight design specifications in critical dimensions. Dark field contact layers are prime candidates for NTD processing due to its high imaging contrast. However, reticles used in NTD processes are highly transparent. The transmission rate of those masks can be over 85%. Consequently, lens heating effects result in a non-trivial impact that can limit NTD usability in a high volume mass production environment. At the same time, Source Mask Optimized (SMO) freeform pupils have become popular. This can also result in untoward lens heating effects which are localized in the lens. This can result in a unique drift behavior with each Zernike throughout the exposing of wafers. In this paper, we present our experience and lessons learned from lens heating with NTD processes. The results of this study indicate that lens heating makes impact on drift behavior of each Zernike during exposure while source pupil shape make an impact on the amplitude of Zernike drift. Existing lens models should be finely tuned to establish the correct compensation for drift. Computational modeling for lens heating can be considered as one of these opportunities. Pattern shapes, such as dense and iso pattern, can have different drift behavior during lens heating.
Higher density on 20nm logic chips require tighter pitches to be implemented not only at critical metal layers, but at BEOL critical VIA layers as well. Smaller pitches on critical via are no longer achievable through the conventional positive tone development (PTD) process. Instead, negative tone development (NTD) is considered, evaluated, and integrated as an alternative, along with the double patterning (DP) method. Additionally, preliminary results on NTD+DP patterning challenges, including patterning verification, are presented in this paper.
Process yield is a critical factor for a success of 300mm manufacturing. Typically, higher yield corresponds to lower
defect counts within the respective processing steps (lithography, etch, plating, and CMP). Within BEOL lithographic
processes, there are issues of defects within same lithographic technology and there are concerns of defects between the
generation of lithographic technologies, for example, immersion, 193nm "dry", and DUV (248nm). In order to have an
effective defect reduction strategy, defects have to be monitored, identified, and analyzed for points of origins. In this
paper, we explore three areas of interests in the BEOL: 1) defects occur between different processing steps, specifically,
after Immersion Lithography, after Reactive Ion Etch (RIE), and after Chemical Mechanical Polish (CMP), 2) defects
after CMP between lithographic technologies (Immersion, Dry, and DUV), and finally 3) defects between different
devices. We were able to find evidence of transferable processing defects.
From the perspectives of IC fabrication simplification, cost reduction, and waste material cutback, it is highly desirable
to combine the traditional pattern formation step (lithographical processes) and the pattern transfer step (etch processes)
into a single step. Photo-imageable spin-on dielectrics (PSOD) render it possible to achieve the aforementioned goal.
However, the bestowed dual functionalities on PSOD put great challenges on the material design and development.
PSOD needs not only to match all the performances of the advanced resists, but also to undertake all the duties of the
dielectrics on the chips. We wish to report our modular approach employing Si-containing materials to address the
challenge and to meet the requirements from the different material roles. This paper will also discuss the investigation
and progress on lithographic performance, cure behaviors, thermal stability, and electrical and mechanical properties.
We report about the development of a thick negative photoresist series, AZ<sup>(R)</sup> EXP 125nXT, and their use in
electroplating levels up to 160 μm thickness. The new photoresist series enables coatings of 5-120 μm with acceptable
uniformity and edge bead in a single coat step. 200 μm photoresist coating was achieved by a double coating processes.
The lithographic performance of the photoresists was evaluated using broad band aligners and steppers. Optimized
lithographic parameters to achieve straight and nearly vertical side wall profiles are reported. The photoresists show not
only excellent adhesion to copper with no surface treatment and electroplating tolerance in a variety of metal plating
solutions, but is also compatible with silicon and gold substrates. The photoresists have been found to be easily stripped
with no residues in solvent based stripper solutions.