The availability of metrology solutions, one of the critical factors to drive leading-edge semiconductor devices and processes, can be confronted with difficulties in the advanced nodes. For developing new metrology solutions, highquality test structures fabricated at specific sizes are needed. Electron-beam direct-write lithography has been utilized to manufacture such samples. However, it can encounter significant-resolution difficulties and require complicated process optimization in sub-10-nm nodes. This study investigates the feasibility and patterning control of metrology test structure fabrication by helium-ion-beam direct-write lithography (HIBDWL). Features down to IRDS 1.5-nm node are resolvable without needing any resolution enhancement technique from the lithography simulation. Further, patterns beyond 1.5-nm node can be achievable with the help of proximity effect correction technique. Preliminary results of simulation demonstrate that HIBDWL can be a promising alternative for fabricating programmed defects (PDs) and test structure to develop advanced metrology solutions in sub-7-nm nodes.
In subwavelength lithography, the printed patterns on the silicon wafer suffer from geometric distortions and different from the original design. These non-rectangular patterns can affect electrical characteristics and circuit performances seriously. In this work, we extend the verification of location-dependent weighting method and further propose three single conventional equivalent gate length (EGL) extraction methods for representing each non-rectangular gate transistor with a single EGL model. These methods are applied to sub-20nm FDSOI circuits to predict the postlithography performances. An in-house Extreme Ultraviolet Lithography (EUVL) simulation tool is utilized for nonrectangular pattern simulation. Shape information is imported to TCAD to construct 3D non-rectangular FDSOI transistor models. The accuracy of the location-dependent weighting method and EGL extraction methods are verified with TCAD circuit simulations. A 2D EGL circuit simulation method in TCAD is proposed instead of 3D EGL method to reduce the simulation time required. Preliminary simulation results indicate that weighting factors can improve the accuracy of electrical characteristics estimation, especially in leakage current analysis. On average, the off-state EGL (EGL<sub>off</sub>) with weightings is good enough. These methods could be used to simulate the non-rectangular transistors applied to sub-20nm FDSOI circuits including 6T-SRAM caused by non-ideal optical effects in industrial processes.
Model-based optical proximity correction (MPOPC) has been well adopted in subwavelength lithography for integrated-circuit manufacturing. Typical MBOPC algorithms involve with iteratively moving the layout polygon edges to reduce the edge placement errors (EPEs) predicted by the lithography model. At each iteration, the amounts of movement are mainly determined by the values of the EPEs and the correction factors (CFs). Since full-chip lithography simulation is very computation intensive, it is highly desirable to minimize the number of iterations for acceptable run times, by selecting suitable CFs. In practical applications, the CFs are usually heuristically determined and applied globally throughout the correction regions. This approach efficiently reduces the EPEs at most of the target points but the entire convergence can be hampered at a relatively small number of hot-spot locations. This work investigates the effectiveness of improving the overall convergence by introducing both global and local CFs, and approaches to utilize machine-learning techniques to estimate the hot-spot locations and associated local CF values.
This work presents a model-based proximity effect correction method and investigates its potential for helium ion beam lithography (HIBL). This method iteratively modulates the shape of pattern by a feedback compensation mechanism until the simulated patterning fidelity satisfied specific constraints. A point spread function is utilized to account for all phenomena involved during the scattering events of incident ion beam particle in the resist. Patterning prediction for subsequent correction process is derived from the energy intensity distribution, as a result of convolution between the point spread function and the pattern, with an adequate threshold. The performance of this method for HIBL is examined through several designed patterns from 15- to 5-nm HP under certain process parameters, including acceleration voltage, resist thickness and sensitivity. Preliminary results show its effectiveness on improving the patterning fidelity of HIBL.
The availability of metrology solutions, one of the key factors to drive leading edge semiconductor devices and processes, can be confronted with difficulties in the advanced node. For developing new metrology solutions, high quality test structures fabricated at specific sizes are needed. Conventional resist-based lithography have been utilized to manufacture such samples. However, it can encounter significant resolution difficulties or requiring complicated optimization process for advanced technology node. In this work, potential of helium ion beam direct milling (HIBDM) for fabricating metrology test structures with programmed imperfection is investigated. Features down to 5 nm are resolvable without implementing any optimization method. Preliminary results have demonstrated that HIBDM can be a promising alternative to fabricate metrology test structures for advanced metrology solutions in sub 10 nm node.