Proc. SPIE. 10146, Advances in Patterning Materials and Processes XXXIV
KEYWORDS: Antireflective coatings, Optical lithography, Metals, Capillaries, Copper, Interfaces, Coating, Photoresist materials, Process control, Semiconducting wafers, Photoresist developing, Back end of line
One of the most critical issues associate with decreasing photo-resist feature size is pattern collapse, and more serious pattern collapse can be easily observed especially in asymmetric pitch environment due to unbalanced capillary stress acting on photo-resist pattern during development rinse step. The pattern collapse would kill product yield in the worse condition. This work investigates the approaches of mitigating the asymmetric pattern collapse behavior, such as adjusting photoresist pattern aspect ratio, applying surfactant during development rinse to reduce the solution surface tension, and altering underlying anti-reflection coating and hard-mask combinations to tailor the photo-resist bottom profile as well as decreasing developer permeation into photo-resist interface. Pattern sizing to resist unbalanced capillary force is also explored in the asymmetric pattern region. Two novel layout methods to mitigate asymmetric dummy pattern collapse were demonstrated and both methods were confirmed to have higher immunity against pattern collapse in asymmetric pitch environment.
As the scaling down of design rule for high-density memory device, the small depth of focus (DoF) budget may be deteriorated by focus leveling errors, which arises in unpredicted reflectivity from multilayer structures on the topographic wafer. The leveling sensors of ASML scanner use near infrared (NIR) range wavelength which can penetrate through most of films using in semiconductor fabrication such as photo-resist, bottom anti reflective coating (BARC) and dielectric materials. Consequently, the reflected light from underlying substructures would disturb leveling sensors from accurate leveling. The different pattern densities and layout characteristics between array and periphery of a memory chip are expected to result in different leveling signals. Furthermore, the process dependent variations between wafer central and edge areas are also considered to yield different leveling performances during wafer exposure.
In this study, lower blind contact immunity was observed for peripheral contacts comparing to the array contacts especially around wafer edge region. In order to overcome this problem, a series of investigations have been carried out. The wafer edge leveling optimization through circuit dependent focus edge clearance (CDFEC) option doesn’t get improvement. Air gauge improved process leveling (AGILE) function of ASML immersion scanner doesn’t show improved result either. The ILD uniformity improvement and step height treatments around wafer edge such as edge exclusion of film deposition and bevel etching are also ineffective to mitigate the blind contact problem of peripheral patterns. Altering the etch hard-mask stack is finally found to be an effective approach to alleviate the issue. For instance, through either containing high temperature deposition advanced patterning film (APF) in the hard-mask or inserting higher opaque film such as amorphous Si in between the hard-mask stack.
Negative tone development (NTD) process benefits the process latitude of dark field features such as contact holes and isolated trenches. Thus the NTD process has been a viable manufacture solution for aggressive-pitch contact patterning. Because the NTD process adopts organic solvent as developer to dissolve the de-protected photo-resist, it may conflict with conventional positive tone development on maximizing the photocell utilization. In the manufacturing implementation of NTD process, the off-line development is the most commonly adopted arrangement to maximize the flexibility of photocell dispatch. Therefore the post exposure bake to development delay (PEBDD) is a concern for thorough investigation to deliver robust NTD process. In this paper, PEBDD induced CD shrinkage was investigated for contact printing to explore the possible mechanism. The resist comparison, ambient contamination verification, baking temperature split of photo-resists were conducted for comparing the PEBDD effect. The experimental results suggested the photo acid concentration and photo acid diffusion are two most critical factors for PEBDD effect. Through the understanding of critical factors for PEBDD, the suitable operation on mitigating PEBDD influence as well as adequate queue time setting were proposed for robust process control.
Overlay performance has been a critical factor for advanced semiconductor manufacturing for years. Over time these
requirements become more stringent as design rules shrink. Overlay mark design and selection are the first two steps of
overlay control, and it is known that different overlay mark designs will have different responses to process conditions.
An overlay mark optimized for traditional process might not be suitable for SADP (self-aligned double patterning)
technology due to changes in lithography and etching process conditions. For instance, the traditional BIB (box-in-box)
target defined by the core mask becomes a template structure in SADP flow, the pitch and cycle of the overlay mark is
further changed after spacer formation and core film removal hence the mark recognition and robustness have been
challenging for the subsequent process layers.
The comprehensive study on the methodology of overlay mark design and selection is still not available for SADP
process. In this paper, various types of overlay marks were designed to comply with the SADP process to get rid of the
weaknesses of traditional targets. TMU (total measurement uncertainty) performance was adopted to determine the
optimal overlay marks for meeting production overlay control requirements in SADP process flow. The results have
suggested the segmented marks outperform to non-segmented marks on image contrast as well as TMU.
SAS (Self-Aligned Source) process has been widely adopted on manufacturing NOR Flash devices. To form the SAS
structure, the compromise between small space patterning and sufficiently removing photo resist residue in topographical
substrate has been a critical challenge as the device scaling down.
In this study, photo simulation, layout optimization, resist processing and tri-layer materials were evaluated to form
defect-free and highly extendible SAS structure for NOR Flash devices. Photo simulation suggested more coherent light
source allowed the incident light to reach the trench bottom that facilitates the removal of photo resist. Mask bias also
benefited the process latitude extension for residue-free SAS printing. In the photo resist processing, both lowering the
SB (Soft Bake) and raising PEB (Post-Exposure Bake) temperature of photo resist were helpful to broaden the process
window but the final pattern profile was not good enough. Thermal flow for pos-exposure pattern shrinkage achieved
small CD (Critical Dimension) patterning with residue-free, however the materials loading effect is another issue to be
addressed at memory array boundary. Tri-layer scheme demonstrated good results in terms of free from residue, better
substrate reflectivity control, enabling smaller space printing to loosen overlay specification and minimizing the poly
gate clipping defect. It was finally proposed to combine with etch effort to from the SAS structure. Besides it is also
promising to extend to even smaller technology nodes.
As the semiconductor feature size continues to shrink, the thickness of photo resist needs to be thinner and thinner to
prevent resist features from collapse. Coupling with the need of high NA lithography for small feature patterning, both
the reflectance control and the etch budget on resist thickness are becoming major challenges for lithographers. One way
to simultaneously satisfy the needs of superior low reflectance, sufficient etch resistance and minimizing the resist
feature collapse is adopting tri-layer lithography scheme.
The tri-layer scheme has been successfully implemented in our manufacturing flow for FEOL (Front-End-of-Line)
application. This work investigated the application of tri-layer scheme to BEOL (Back-End-of-Line) AlCu patterning.
One critical problem met in this application is the defect that majorly originates from wafer edge after AlCu patterning.
The defects were finally ascribed to the hump formation of Si-rich hard-mask by EBR (Edge Bead Removal) process.
The hump of Si-rich hard-mask yields etch masking behavior during AlCu etch accordingly leads to pattern bridging or
peeling of inorganic hard-mask after AlCu patterning. To reduce the defect, several evaluations were made to suppress
the hump formation, including the EBR optimization, bake condition of Si-rich hard-mask, film stacking architecture of
tri-layer by EBR rinse and surfactant additive added Si-rich hard-mask. A synergy effect among process factors has been
proposed to effectively fix the defect problem around wafer edge.
Contact hole within a NOR FLASH memory array is one of the most challenging features to print in the semiconductor
manufacturing. It has been the key limiter of NOR FLASH memory scaling due to the difficulties involved in patterning
the one-dimensional contact arrays and extremely stringent contact to gate overlay constraints.
In this study, DPT (Double Patterning Technology) by ArF dry process was introduced for patterning NOR FLASH
memory contact arrays. This approach has demonstrated a contact patterning with extremely low optical proximity effect
for 50nm half-pitch with satisfied lithography process latitude and especially the circular contact shape can be
maintained without compromise of NOR FLASH cell area. The novel hard mask scheme was the key enabler for this
contact double patterning and this approach can be easily extended to ArF immersion lithography as a promising option
for contact formation in leading-edge memory products.
AlCu PVD (Physical Vapor Deposition) induced overlay shift has been a critical concern for non-damascene
metallization process to tackle with the ever decreasing overlay tolerances. In this study, a new approach was
demonstrated to effectively eliminate the AlCu PVD induced overlay shift. With measuring the metal-to-contact
registration before the metal deposition and feeding forward the values for metal-to-contact overlay compensation at the
metal photo process, the metal-induced shift can be optimally managed. Besides, an investigation was also carried out to
figure out the suitable measurement target with least sensitive to process parameter variations at after contact etch, after
contact W CMP and after metal etch. As a consequence, the conventional wide-trench overlay target has been identified
to be the more susceptible to the process variation and easily results in measurement reading error. Compared to the
conventional wide-trench target, a 0.2um width narrow trench target performed the better mark integrity for our feed-forward
compensation approach. Finally, the feed-forward compensation in combination with narrow width overlay
mark has demonstrated its effectiveness on managing the AlCu-PVD induced overlay shift.