A method to perform Optical Proximity Correction (OPC) model calibration that is also sensitive to lithography failure modes and takes advantage of the large field of view (LFoV) e-beam inspection, is presented. To improve the coverage of the OPC model and the accuracy of the after development inspection (ADI) pattern hotspots prediction - such as trench pinching or bridging in complex 2D routing patterns - a new sampling plan with additional hotpot locations and the corresponding contours input data is introduced. The preliminary inspected hotspots can be added to the traditional OPC modeling flow in order to provide extra information for a hotspot aware OPC model. A compact optical/resist 3D modeling toolkit is applied to interpret the impact of photoresist (PR) profiles, as well as accurate predictions of hotspot patterns occurring at the top or bottom of the PR. A contour-based modeling flow is also introduced that uses a site or edge based calibration engine, to better describe hotspot locations in the hotspot aware OPC model calibration. To quantify the improvement in pattern coverage in the modeling flow, feature vectors (FVs) analysis and comparisons between the conventional and the hotspot aware OPC models is also presented. The time and cost of using conventional Critical Dimension Scanning Electron Microscope (CD-SEM) metrology to measure such a large amount of CD gauges are prohibitive. By contrast, using LFoV e-beam inspection with improved training algorithm to extract fine contours from wafer hotspots, a hotspot aware OPC model can predict ADI hotspots with a higher capture rate as compared to main feature OPC model. Presumably, a hotspot-aware modeling flow based on LFoV images/contours not only benefits users by improving the capture rate of the lithography defects, but also brings the advantages to the failure mode analysis for the post-etch stage.
The methods to calculate the probability of success/failure of EUV lithography (EUVL) processes are presented. The success of an EUVL process is defined as a complete removal of the resist material within one set of designated volumes and a complete retention of the resist material within another set of designated volumes in the resist film. We demonstrate that, under certain assumptions, the probability calculation reduces to the well-known problem of calculation of probability of excursion of a certain Gaussian random field. The methods to calculate the probability of success/failure of a lithographic process are presented, including the Monte-Carlo methods, methods based on factorization of a covariance matrix, methods based on Mahalanobis distance, and the methods using Rice’s formula and its variations. A particular attention is paid to the methods applicable to full chip OPC and OPC verification. The results from the proposed methods are tested in simulations and by comparison with experimental data.
The method to perform Optical Proximity Correction (OPC) model calibration with contour-based input data from both small field of view (SFoV) and large field of view (LFoV) e-beam inspection is presented. For advanced OPC models - such as Neural Network Assisted Models (NNAM) , pattern sampling is a critical topic, where pattern feature vectors utilized in model training, such as image parameter space (IPS) is critical to ensure accurate model prediction [2-5]. In order to improve the design space coverage, thousands of gauges with unique feature vector combinations might be brought into OPC model calibration to improve pattern coverage. The time and cost in conventional Critical Dimension Scanning Electron Microscope (CD-SEM) metrology to measure this large amount of CD gauges is costly. Hence, an OPC modeling solution with contourbased input has been introduced . Built on this methodology, a single inspection image and SEM contour can include a large amount of information along polygon edges in complex logic circuit layouts. Namely, a better feature vector coverage could be expected . Furthermore, much less metrology time is needed to collect the OPC modeling data comparing to conventional CD measurements. It is also shown that by utilizing large field 2D contours, which are difficult to characterize by CD measurements, in model calibration the model prediction of 2D features is improved. Finally, the model error rms of conventional SFoV modeling and LFoV contour modeling between SEM contours and simulation results are compared.
EUV lithography has enabled shrinking feature sizes up until iN7 using the current Ta-based mask absorber. As we explore next generation nodes, iN5 and beyond, the mask three dimensional (M3D) effects will have a significant impact at wafer level due to the mask architecture, and the oblique illumination angles [1-2]. In order to mitigate these effects, we explore the optical performance of two alternative mask absorber candidates; a High-k absorber and an attenuated phase shifting mask absorber (AttPSM) and compare them to the current Ta-based mask absorber. We evaluate and compare the mask absorbers for memory and logic layers by lithographic source-mask optimization (SMO) using Mentor’s pxSMO tool with ASML’s NXE3400B settings. For memory, contact-holes are simulated using dark-field mask whereas the pillars case is simulated with bright field mask to evaluate bright field as a mask option for EUV with alternative mask absorbers. For logic case, we test these absorbers on iN5 self-aligned block (SAB) layer . The self-aligned block layer is also simulated by adding sub-resolution assist features (SRAFs) to predict the insertion point of SRAFs for logic designs and see if new mask absorber material can reduce the need of SRAF insertion. SMO for memory case shows higher common depth of focus (cDOF) and lower edge placement error (EPE) for High-k absorber over the conventional TaBN mask absorber, whereas significant gain in normalized image log slope (NILS) is observed for the AttPSM absorber. The logic case also has better performance in terms of common depth of focus (cDOF), NILS, EPE mask error enhancement factor (MEEF) and process variation band (PV-band). Adding SRAF’s to iN5 SAB improves the PV-band and image shift through focus for all three cases.
As the process generation migrate to advanced and smaller dimension or pitch, the mask
and resist 3D effects will impact the lithography focus common window severely because of
both individual depth-of-focus (iDOF) range decrease and center mismatch. Furthermore,
some chemical or thermal factors, such as PEB (Post Exposure Bake) also worsen the usable
depth-of-focus (uDOF) performance. So the mismatch of thru-pitch iDOF center should be
considered as a lithography process integration issue, and more complicated to partition the
3D effects induced by optical or chemical factors.
In order to reduce the impact of 3D effects induced by both optical and chemical issues, and
improve iDOF center mismatch, we would like to propose a mask absorber thickness offset
approach, which is directly to compensate the iDOF center bias by adjusting mask absorber
thickness, for iso, semi-iso or dense characteristics in line, space or via patterns to enlarge
common process window, i.e uDOF, which intends to provide similar application as
Flexwave (ASML trademark).
By the way, since mask absorber thickness offset approach is similar to focus tuning or
change on wafer lithography process, it could be acted as the process tuning method of
photoresist (PR) profile optimization locally, PR scum improvement in specific patterns or to
modulate etching bias to meet process integration request.
For mass production consideration, and available material, current att-PSM blank, quartz,
MoSi with chrome layer as hard-mask in reticle process, will be implemented in this
experiment, i.e. chrome will be kept remaining above partial thru-pitch patterns, and act as the
absorber thickness bias in different patterns. And then, from the best focus offset of thru-pitch
patterns, the iDOF center shifts could be directly corrected and to enlarge uDOF by increasing
the overlap of iDOF. Finally, some negative tone development (NTD) result in line patterns will
be demonstrated as well.
In advanced 20nm and below technology nodes, the mask enhanced error factor (MEEF) plays an important rule due to the request of stable process control and quality of mask manufacture. It provides us an effective parameter to analyze the process window for lithography. In advanced nodes, MEEF criterion becomes more important than previous nodes because very tight process tolerance is requested, especially in OPC and mask capability control. Therefore, we have to do further studies on this topic. In the simple line/trench design layers (for example: Active and poly), the MEEF is easy to be defined because mask bias is isotropic. However, in the complicated two-dimensional (2D) design layers (for example: Contact and Mvia), they are hard to be defined a suitable definition of MEEF. In the first part, we used the global bias to calculate the MEEF on all patterns. It makes calculation easier to compare with other patterns which are different shapes. However, when we inspected the 2D line-end patterns on the wafer, we found the significant differences between the MEEF of wafer data and aerial simulation. In order to clarify this issue, we perform series simulation studies of the line-end MEEF. Then we knew that it came from the different bias strategies. Furthermore, the simulation studies show that the line-end MEEF of non-preferable orientation is very sensitive to mask X/Y ratio bias due to strong OAI optical behavior by the SMO source. As a result, a new point of view of 2D MEEF is suggested according to physical mask CD error measurement data. In this study, we would find a better description of the MEEF than traditional one for lithographic process development on 2D region.
As semiconductor process technology moves to smaller dimension, RET (resolution enhancement technology)
becomes more and more important, especially in low k1 processes. From 28nm node to 20nm node, the k1 becomes
smaller with smaller dimension and pitch because exposure tool can provide larger NA (numerical aperture) or smaller
exposure wavelength. SMO (source mask optimization) is a RET solution for low k1 process and provide better
lithographic common process window in single exposure technology.
Base on our studies of aerial image simulation and real wafer experiments on 20nm node, SMO could provide a better
solution for 20nm node with 1.35 NA and 193nm exposure wavelength than the other RET sources (Quasar, C-Quad.,
In the first step, the concerned patterns are important for the optimization because the main purpose of SMO is to
obtain better performance in those. Through SMO iteration, we can find out a better source for our design rule and
concerned patterns (like SRAM, and Small Island patterns). Then, we evaluate whether the simulation results can
provide enough accuracy from real wafer data. Base on this study, we can develop a suitable SMO process for 20nm
In this paper, we will show the optical theory, simulation result and wafer performance of SMO technology.