In an advanced IC fab, reticle inspection issues are critical as even one killer defect on the reticle can potentially affect thousands of wafers. Human errors such as defect mis-classification may lead to 70% of reticle issues that may affect production efficiency or even impact yield. With the adoption of RET techniques like aggressive OPC and SRAF combined with increasing MEEF and smaller defects, reticle dispositioning is becoming even harder and very time consuming in production. Even an experienced engineer may make a mistake especially when dealing with 40nm and below design nodes. The concept of automation to prevent mistakes in operation has been promoted for many years but a comprehensive solution which covers intelligent task assignment and auto reticle dispositioning in volume production has been missing. Working together with KLA, USCXM proposed a detailed methodology to overcome the above difficulties. From the very beginning, USCXM used Systematic Auto Recipe Creation (SARC) to create recipes for reticle inspections even before the reticles arrived in the fab. Also, an “OHT taxi mode” to improve pod utilization combined with the Reticle Management System (RMS) decision tree algorithm intelligently determined reticle inspection frequency based on wafer requirement and tool redundancy. Finally, USCXM automated final reticle dispositioning steps, such as, auto-releasing or auto-holding the reticle based on KLA’s Reticle Analyzer (RA) results. The overall implementation resulted in 25% improvement in inspection capacity and 50% reduction in operational cost compared to the traditional flow. Further, 92% accuracy for reticle auto-dispositioning was achieved with zero under-estimation. This integrated flow has proven to be invaluable for USCXM and is now deployed in full volume reticle manufacturing production.
According to the ITRS roadmap, semiconductor industry drives the 193nm lithography to its limits, using techniques like Double Pattern Technology (DPT), Source Mask Optimization (SMO) and Inverse Lithography Technology (ILT). In terms of considering the photomask metrology, full in-die measurement capability is required for registration and overlay control with challenging specifications for repeatability and accuracy. <p> </p>Double patterning using 193nm immersion lithography has been adapted as the solution to enable 14nm technology nodes. The overlay control is one of the key figures for the successful realization of this technology. In addition to the various error contributions from the wafer scanner, the reticles play an important role in terms of considering lithographic process contributed errors. Accurate pattern placement of the features on reticles with a registration error below 4nm is mandatory to keep overall photomask contributions to overlay of sub 20nm logic within the allowed error budget.<p> </p> In this paper, we show in-die registration errors using 14nm DPT product masks, by measuring in-die overlay patterns comparing with regular registration patterns. The mask measurements are used to obtain an accurate model to predict mask contribution on wafer overlay of double patterning technology.