Traditionally, product development for reticle defect inspection mostly addressed operational requirements of the mask shops with highly individualized manufacturing. As a result, limited automation capability was available as compared to the standards in wafer production. Wafer fabs are guided by completely different conditions. Thousands of active reticles exist in a single fab requiring frequent re-inspections without interruption of wafer exposures. This requires high throughput of inspection tools, smart management of tool fleet, sophisticated scheduling and in-time execution of reticle inspections linked to the wafer manufacturing. The paper reports about the successful implementation of fully automated reticle defect inspection in a high-volume advanced logic fab. Automation scenarios - created based on existing SEMI standards - included inspection scheduling, reticle transport and inspection tool operation. A considerable productivity gain for the operation of Lasertec MATRICS X700 series inspection tools was obtained. Based on the learning throughout implementation, the requirements to the
automation capability and tool operation as well as adjustments to working procedures are discussed.
Backside defects are out of focus during wafer exposure by the mask thickness and cannot be directly imaged on wafer.
However, backside defects will induce transmission variation during wafer exposure. When the size of backside defect is
larger than 200 microns, the shadow of such particles will locally change the illumination conditions of the mask
patterns and may result in a long range critical dimension (CD) variation on wafer depending on numerical aperture
(NA) and pupil shape. Backside defects will affect both wafer CD and critical dimension uniformity (CDU), especially
for two-dimensional (2D) structures. This paper focuses on the printability of backside defects on contact layer using
annular and quadrupole illumination mode, as well as using different reticle blank material. It also targets for gaining
better understanding of critical sizes of backside defects on contact layer for different reticle blanks.
We have designed and manufactured two test reticles with repeating patterns of 28nm and 40nm technology node of
contact layers. Programmed chrome defects of varying size are placed on the backside opposite to the repeating front
side patterns in order to measure the spatial variation of transmission and wafer CD. The test mask was printed on a bare
silicon wafer, and the printed features measured for size by spatial sampling. We have investigated two contact layers
with different illumination conditions. One is advance binary with single exposure; another is phase shift mask with
double exposure. Wafer CD variation for different backside defect sizes are demonstrated for the two contact layers. The
comparison between backside defect size with inter-field and intra-field CD variation is also discussed.
Reticles are contaminated during its lifetime and can catch particles as large as several tens of microns. Such defects on
the backside of photomasks are usually considered as uncritical and thus do not receive much attention. Backside defects
are out of focus by the mask thickness during wafer exposure and cannot be directly imaged on wafer. However, the
shadow of the defects changes the local illumination of the mask patterns and may result in spatial variation of critical
dimension (CD) on wafer depending on numerical aperture (NA) and pupil shape.
There have been only a few investigations on printability of backside defects in the past, and no data are available for the
most advanced technology nodes. Reticles are regularly inspected for particles on the glass side in the wafer fab but
limits for acceptable defect size are based on estimations. Detection of non-acceptable particles causes exposed wafers
being either delayed or reworked with impact on throughput and cost performance. It is therefore important to gain better
understanding of critical sizes of backside defects and of appropriate detection capabilities.
We have designed and manufactured a test mask with repeating patterns of 20nm, 28nm and 40nm technology node
ranging from contact and line/space critical layers to non-critical implant layers. Programmed chrome defects of varying
size are placed on the backside of the mask opposite to the repeating front side patterns in order to measure the spatial
variation of transmission and wafer CD caused by the backside defects. The test mask was printed on a bare Silicon
wafer and the size of printed features was measured by spatial sampling. Wafer CD variation for different backside
defect sizes are demonstrated and compared for 28nm node first metal layer.
Although the opaque chrome defects on the backside do not behave like real particles they aim on deriving a print
threshold for backside particles based on actual wafer data. After such critical size of backside defects is obtained the
reticle was also utilized to investigate the detection ability of backside defects by defect inspection of the reticle.
Reticle process of record (POR) sometimes needs fine tuning for some reasons such as multiple layer process, better
critical dimension uniformity (CDU) or new etch chamber. The sidewall angle and corner rounding will be varied due to
the reticle processing tuned comparing to previous POR. However, because the reticle critical dimension (CD)
measurement is based on middle side lobe measurement or other algorithm, the reticle CD cannot reflect the changes of
reticle sidewall angle and corner rounding variation which are critical for 65nm node and below. Each of the scanner,
wafer process, reticle and metrology tool contributes to the intra-field wafer CD. Normally, the reticle contribution to the
wafer CDU should be as small as possible, that is less than 33%. By averaging all wafer CD of individual features to
obtain a wafer CD reference independent of feature location and wafer die, the correlation of wafer measurement to
target (MTT) and reticle MTT can be obtained. The correlation can accurately qualify and monitor the tuning processing
We have manufactured two masks for active layer of 65nm tech node by different reticle process. One used the original
POR process of active layer, while another used multi-layer-reticle (MLR) process. The correlations between wafer
CDU and reticle CDU of these reticles are demonstrated for both isolated and dense features in vertical and horizontal
direction, respectively. Similar experiments were implemented and the correlations for both dense and isolated structures
are demonstrated as well, for two different POR process for first metal layer of 40nm tech node. Referring to the wafer
and reticle MTT correlation, the contribution of reticle CDU to wafer CDU can be used as an evaluation methodology
for reticle processing. The wafer and reticle CDU correlations for 45nm node poly and contact layers POR process are
A host of complementary imaging techniques (Scanning Electron Microscopy), surface
analytical technique (Auger Electron Spectroscopy, AES), chemical analytical and
speciation techniques (Grazing Incidence Reflectance Fourier-Transform Infrared
Spectroscopy, GIR-FTIR; and Raman spectroscopy) have been assessed for their
sensitivity and effectiveness in analyzing contamination on three EUV reticles that were
contaminated to varying degrees. The first reticle was contaminated as a result of its
exposure experience on the SEMATECH EUV Micro Exposure Tool (MET) at Lawrence
Berkeley National Laboratories, where it was exposed to up to 80 hours of EUV radiation.
The second reticle was a full-field reticle, specifically designed to monitor molecular
contamination, and exposed to greater than 1600J/cm2 of EUV radiation on the ASML Alpha Demo Tool (ADT) in Albany Nanotech in New York. The third reticle was intentionally contaminated with hydrocarbons in the Microscope for Mask Imaging and
Contamination Studies (MIMICS) tool at the College of Nanoscale Sciences of State
University of New York at Albany. The EUV reflectivities of some of these reticles were
measured on the Advanced Light Source EUV Reflectomer at Lawrence Berkeley
National Laboratories and PTB Bessy in Berlin, respectively. Analysis and
characterization of thin film contaminants on the two EUV reticles exposed to varying
degrees of EUV radiation in both MET and ADT confirm that the two most common
contamination types are carbonization and surface oxidation, mostly on the exposed areas
of the reticle, and with the MET being significantly more susceptible to carbon
contamination than the ADT. While AES in both surface scanning and sputter mode is
sensitive and efficient in analyzing thin contaminant films (of a few nanometers), GIRFTIR
is sensitive to thick films (of order of a 100 nm or more on non-infra-red reflecting
substrates), Raman spectroscopy is not compatible with analyzing such contaminants because of laser-induced evaporation of the contaminant film. SEM and EUV reflectometry are effective in quantifying the impact of contamination on imaging performance and reflectivity, respectively.
We are evaluating the readiness of extreme ultraviolet (EUV) lithography for insertion into production at the 15 nm
technology node by integrating it into standard semiconductor process flows because we believe that device integration
exercises provide the truest test of technology readiness and, at the same time, highlight the remaining critical issues. In
this paper, we describe the use of EUV lithography with the 0.25 NA Alpha Demo Tool (ADT) to pattern the contact and
first interconnect levels of a large (~24 mm x 32 mm) 22 nm node test chip using EUV masks with state-of-the-art
defectivity (~0.3 defects/cm2). We have found that: 1) the quality of EUVL printing at the 22 nm node is considerably
higher than the printing produced with 193 nm immersion lithography; 2) printing at the 22 nm node with EUV
lithography results in higher yield than double exposure double-etch 193i lithography; and 3) EUV lithography with the
0.25 NA ADT is capable of supporting some early device development work at the 15 nm technology node.
We describe the imaging and characterization of native defects on a full field extreme ultraviolet (EUV) mask, using
several reticle and wafer inspection modes. Mask defect images recorded with the SEMATECH Berkeley Actinic
Inspection Tool (AIT), an EUV-wavelength (13.4 nm) actinic microscope, are compared with mask and printed-wafer
images collected with scanning electron microscopy (SEM) and deep ultraviolet (DUV) inspection tools.
We observed that defects that appear to be opaque in the SEM can be highly transparent to EUV light, and inversely,
defects that are mostly transparent to the SEM can be highly opaque to EUV. The nature and composition of these defects, whether they appear on the top surface, within the multilayer coating, or on the substrate as buried bumps or pits, influences both their significance when printed, and their detectability with the available techniques. Actinic inspection quantitatively predicts the characteristics of printed defect images in ways that may not be possible with non-EUV techniques.
This paper assesses the readiness of EUV masks for pilot line production. The printability
of well characterized reticle defects, with particular emphasis on those reticle defects that
cause electrical errors on wafer test chips, is investigated. The reticles are equipped with
test marks that are inspected in a die-to-die mode (using DUV inspection tool) and
reviewed (using a SEM tool), and which also comprise electrically testable patterns. The
reticles have three modules comprising features with 32 nm ground rules in 104 nm pitch,
22 nm ground rules with 80 nm pitch, and 16 nm ground rules with 56 nm pitch (on the
wafer scale). In order to determine whether specific defects originate from the substrate,
the multilayer film, the absorber stack, or from the patterning process, the reticles were
inspected after each fabrication step. Following fabrication, the reticles were used to print
wafers on a 0.25 NA full-field ASML EUV exposure tool. The printed wafers were
inspected with state of the art bright-field and Deep UV inspection tools. It is observed
that the printability of EUV mask defects down to a pitch of 56 nm shows a trend of
increased printability as the pitch of the printed pattern gets smaller - a well established
trend at larger pitches of 80 nm and 104 nm, respectively. The sensitivity of state-of-the-art
reticle inspection tools is greatly improved over that of the previous generation of
tools. There appears to be no apparent decline in the sensitivity of these state-of-the-art
reticle inspection tools for higher density (smaller) patterns on the mask, even down to
56nm pitch (1x). Preliminary results indicate that a blank defect density of the order of
0.25 defects/cm2 can support very early learning on EUV pilot line production at the 16nm node.
Molecular contamination risk to an EUV reticle exposed to up to 1600J/cm2 of 13.5 nm
EUV radiation in ASML Alpha Demo Tool (ADT) is negligible. Carbon film (< 0.5 nm)
deposition and oxidation (surface oxides ~1 nm) are the two main molecular
contaminants observed on this EUV reticle. These results run counter to recent empirical
results obtained from EUV micro-exposure tools (MET) which suggest that molecular
contamination of EUV reticles, even at the very low partial pressures expected in the
exposure chamber of EUV exposure tools, poses challenges in the implementation of
EUV lithography in large-scale volume manufacturing of devices. To assess the
molecular contamination risk to the use and lifetime of a given EUV reticle, we
monitored the contamination buildup on a specially designed reticle during one year as it
was exposed on ASML ADT located in Albany, New York. The reticle was analyzed
with a suite of complementary surface analytical technique (such as Auger Electron
Spectroscopy, AES) and chemical analytical techniques (such as Grazing Incidence
Reflection Fourier Transform Infra-red Spectroscopy, GIR-FTIR), as well as imaging
technique (such as Scanning Electron Microscopy). The influence of molecular
contamination on the reflectivity of this reticle was measured at the Lawrence Berkeley
Advanced Light Source EUV reflectometry. The differences in the contamination
outcome of EUV reticles exposed in ASML ADT and MET may be related to the
implementation of active contamination mitigation schemes in ADT and the lack of similar schemes in METs.
Reticle defectivity was evaluated using two known approaches: direct reticle inspection and the inspection of the
wafer prints. The primary test vehicle was a reticle with a design consisting of 45 nm and 60 nm comb and
serpentine structures in different orientations. The reticle was inspected in reflected light on the KLA 587 in a die-todie
and a die-to-database mode. Wafers were exposed on a 0.25 NA full-field EUV exposure tool and inspected on a
KLA 2800. Both methods delivered two populations of defects which were correlated to identify coinciding
detections and mismatches. In addition, reticle defects were reviewed using scanning electron microscopy (SEM) to
assess the printability. Furthermore, some images of the defects found on the 45 nm reticle used in the previous
study  were collected using actinic (EUV) microscopy. The results of the observed mask defects are presented and
discussed together with a defect classification.
We have used ASML's full field step-and-scan exposure tool for extreme ultraviolet lithography (EUVL), known as an
Alpha Demo Tool, to investigate one of the critical issues identified for EUVL, defectivity associated with EUV masks.
The main objective for this work was to investigate the infrastructure currently in place to examine defects on a EUV
reticle and identify their consequence in exposed resist. Unlike many previous investigations this work looks at
naturally occurring defects in a EUV exposed metal layer from a 45 nm node device. The EUV exposure was also
integrated into a standard process flow where the other layers were patterned using more conventional 193-nm
This presentation correlates reticle level defectivity to resulting wafer exposures. Defect inspection data from both the
28xx family of KLA-Tencor wafer inspection tool and Terascan reticle inspection tools are presented. Defect
populations were characterized with a KLA 5200 Review SEM. Observed defectivity modes were analyzed using both
conventional defect inspection methodology as well as advanced techniques in order to gain further insight. We find
good correlations between reticle level defects and the resulting wafer exposure defects.
At photomask manufacturing, post pellicle inspection suffers from an interference of pellicle size and height dimensions
with the inspection equipment requirements. This pellicle shadow causes nonreliable inspection results. The evolution
of this effect as well as similar potentially upcoming effects during other lithography processes need to be understood in
order to identify potential problems ahead of time and guide the industry accordingly. The study recommends
standardizing pellicle size and height dimensions in order to coordinate the required changes at scanner, mask inspection,
mask metrology and pellicle vendors in the near and long term. Since frequent changes in other pellicle properties are
expected over time to fulfill the requirements for high NA lithography and haze reduction, a standard in pellicle
dimensions will also help controlling the complexity of pellicle variations.
Defect inspection is one of the major challenges in the manufacturing process of photomasks. The absence of any
printing defect on patterned mask is an ultimate requirement for the mask shop, and an increasing effort is spent in order
to detect and subsequently eliminate these defects. Current DUV inspection tools use wavelengths five times or more
larger than the critical defect size on advanced photomasks. This makes the inspectability of high-end mask patterns
(including strong OPC and small SRAF's) and sufficient defect sensitivity a real challenge. The paper evaluates the
feasibility of inspecting the printed wafer as an alternative way for the high-sensitivity defect inspection of photomasks.
Defects originating in the mask can efficiently be filtered as repeated defects in the various dies on wafer. Using a
programmed-defect mask of 65-nm technology, a reliable detection of the printing defects was achieved with an
optimized inspection process. These defects could successfully be traced back to the photomask in a semi-automated
process in order to enable a following repair step. This study shows that wafer inspection is able to provide a full defect
qualification of advanced photomasks with the specific advantage of assessing the actual printability of arbitrary defects.
Pushing the limits of optical lithography by immersion technology requires ever smaller feature sizes on the reticle. At the same time the k1-factor will be shifted close to the theoretical limit, e.g. the OPC structures on the reticle become very aggressive. For the mask shop it is essential to manufacture defect free masks. The minimum defect size, which needs to be found reliably, becomes smaller with decreasing feature sizes. Consequently optical inspection of masks for the 45nm node and below will be challenging.
In this paper the limits of existing KLA inspection tools were investigated by systematic inspection of different structures without and with programmed defects. A test mask with isolated and dense lines/space patterns including programmed defects was manufactured, completely characterized by CD-SEM and inspected with state-of-the-art inspection system. AIMSTM measurements were used to evaluate the defect printing behavior. The analysis of the measurement data gives an input for requirements of reticle inspection of upcoming 45nm node and beyond.
Defect-free masks are one of the top issues for enabling EUV lithography at the 32-nm node. Since a defect-free process cannot be expected, an understanding of the defect printability is required in order to derive critical defect sizes for the mask inspection and repair. Simulations of the aerial image are compared to the experimental printing in resist on the wafer. Strong differences between the simulations and the actual printing are observed. In particular the minimum printable defect size is much larger than expected which is explained in terms of resist resolution. The defect printability in the current configuration is limited by the resist process rather than the projection optics.
We report on a method to produce any type of phase-shift masks for EUV lithography. We have successfully fabricated an unattenuated phase-shift mask consisting of phase patterns and confirmed the expected performance of such a mask through resist printing at λ=13.3 nm. Finally actinic metrology reveals that these etched-multilayer masks, left without a capping layer, tend to degrade over time.
In mask fabrication pattern-inspection is a key step. It ensures mask quality is being met according to the customer defect criteria. Tool selection is based on a comparison between customer requirements and tool capabilities. Inspection tools are typically specified by a minimum feature size at which a certain minimum defect size can be achieved. Mask shops on the contrary manufacture masks for a wide range of feature and defect sizes. As a consequence detailed tool characterizations are needed, which go beyond the typical tool specifications. In this paper characterization results for three KLA 576 inspection systems are presented. Defect sensitivity was studied for the pixels named P125 and P90 in combination with the so-called die-to-die (D2D) and die-to-database (D2Db) algorithms using standardized programmed defect masks. The good correlation of the qualification data made modeling of the tool behavior possible. The modeling parameters were used to compare tool-to-tool and plate-to-plate variations as well as specified and actual tool performance. For a variety of mask types, such as Chrome-on-Glass (COG) masks, embedded phase shift masks at a lithography wavelength of 193 nm (EPSM-193), and extreme ultra-violet (EUV) masks, the optical contrast was studied over a wide range of feature sizes. From the resultant data material dependence and image contrast below the minimum feature size was evaluated.
Extreme Ultraviolet Lithography (EUVL) is the favourite next generation lithography candidate for IC device manufacturing with feature sizes beyond 32nm.
Different stacks and manufacturing concepts have been published for the fabrication of the reflective EUVL masks.
Patterning processes for two different absorber-buffer combinations on top of the reflective multi layer mirror have been developed. A TaN/SiO2 absorber-buffer stack was provided by supplier A and TaBN/Cr by supplier B. In addition both absorbers were covered by an anti reflective coating (ARC) layer. An e-beam patterned 300nm thick film of Fuji FEP171 was used as resist mask.
We optimized the etching processes for maximum selectivities between absorber, buffer and capping layers on the one hand and rectangular profiles and low etch bias on the other hand. While both TaN based absorbers have been dry etched in an UNAXIS mask etcher III, wet and dry etch steps have been evaluated for the two different buffer layers. The minimum feature size of lines and holes in our test designs was 100nm.
After freezing the processes a proximity correction was determined considering both, the influence of electron scattering due to e-beam exposure and the influence of the patterning steps. Due to the correction an outstanding linearity and iso/dense bias on different test designs was achieved.
Various masks for printing experiments at the small-field Micro Exposure Tool (MET) in Berkeley and the fabrication of the ASML α-tool setup mask within the European MEDEA+ EXTUMASK project were done using the developed processes.
Finally, we will compare and discuss the results of the two stack approaches.
Due to the non-telecentricity of the EUV illumination, the EUV mask flatness budget dictates the use of an electrostatic chuck in the exposure tool. Since the mask backside flattening provided by the electrostatic chuck in the exposure tool is very different from the 3-point mounts currently employed to hold reticles in pattern generation and registration measurement tools, this raises the question of which mounting techniques to apply in future patterning and registration tools. In case drastic changes need to be made to the tool configurations, it is important to know, and as early as possible, whether backside chucking of reticles, via an electrostatic or vacuum chuck, is absolutely required or if a 3-point mounting scheme can suffice in these tools. Using finite element simulations, the effects on EUV mask image placement of stressed layers and their patterning, as well as substrate and chuck non-flatness were predicted for these different conditions. The results can be used to calculate image placement error budgets and determine what substrate and blank specifications are needed for the implementation of EUV at the 32-nm node.
Several masks have been fabricated and exposed with the small-field Micro Exposure Tool (MET) at the Advanced Light Source (ALS) synchrotron in Berkeley using EUV radiation at 13.5 nm wavelength. Investigated mask types include two different absorber masks with TaN absorber as well as an etched multilayer mask. The resulting printing performance under different illumination conditions were studied by process window analysis on wafer level. Features with resolution of 60 nm and below were resolved with all masks. The TaN absorber masks with different stack thicknesses showed a similar size of process window. The differences in process windows for line patterns were analyzed for 60 nm patterns. The implications on the choice of optimum mask architecture are discussed.
The interface roughness of EUV mask multilayers was taken into account for the numerical calculation of blank reflectance, and models for the growth of oxide on Si capping layers were proposed and evaluated. The simulations were then checked and validated with reflectometry measurements at different steps of the mask blank processing as well as for various angles of incidence, and ellipsometry data on layer thickness. The benchmarked models made it possible to characterize EUV mask blank Mo/Si multilayers (period, thickness ratio, number of bilayers), as well as Si capping layers and native oxide layers from reflectivity measurements. This enabled the study, via a combination of experiments and simulations, of the growth of SiO2 layers, bringing deeper understanding into this phenomenon. Finally, the simulations were used to more properly optimize multilayers and quantify the influence of the exposure tool illumination numerical aperture. Having successfully matched reflectivity data around the actinic wavelength, it was also possible to extend the models to inspection wavelengths in order to predict inspection contrast values.
Three different architectures were compared as candidates for EUV lithography masks. Binary masks were fabricated using two different stacks of absorber materials and using a selective etching process to directly pattern the multilayer of the mask blank. To compare the effects of mask architecture on resist patterning, all three masks were used to print features into photoresist on the EUV micro-exposure tool (MET) at Lawrence Berkeley National Laboratory. Process windows, depth of focus, mask contrast at EUV, and horizontal and vertical line width bias were use as metrics to compare mask architecture. From printing experiments, a mask architecture using a tantalum nitride absorber stack exhibited the greatest depth of focus and process window of the three masks. Experimental results obtained using prototype masks are discussed in relation to simulations. After accounting for CD biasing on the masks, similar performance was found for all three mask architectures.
Extreme Ultraviolet Lithography (EUVL) is the favourite next generation lithography candidate for IC device manufacturing with feature sizes beyond 32nm. The SiO2 buffer dry etching is a crucial step in the manufacture of the EUV mask due to stringent CD and reflectance requirements. In contrast to conventional chromium absorber layers new absorber materials e.g. TaN require an adjustment of the SiO2 buffer etch chemistry and process parameters to avoid a strong influence on the initial absorber profile and thickness. We have developed a SiO2 buffer dry etch process that uses the structured TaN absorber as masking layer. A laser reflectometer was used during the SiO2 dry etch process for process control and endpoint detection. Different dry etch processes with SF6/He, CF4 and CHF3/O2 etch chemistry have been evaluated and compared with regard to TaN- and SiO2- etch rate, TaN- and SiO2 etch profile and Si capping layer selectivity. We focused our work on minimum feature sizes and simultaneous etching of different line (e.g. dense- and isolated lines) and hole patterns. Line and contact hole structures with feature sizes down to 100nm have been realized and characterized in a SEM LEO 1560. The whole mask patterning process was executed on an advanced tool set comprising of a Leica SB 350 variable shaped e-beam writer, a blank coater Steag HamaTech ASR5000, a developer Steag HamaTech ASP5000 and a two chamber UNAXIS mask etcher III.
Currently, EUV lithography targets for sub-50 nm features. These very small feature sizes are used for reflective illumination and impose great challenges to the mask maker since they do not allow a simple downscaling of existing technologies. New material combinations for absorber and buffer layer of EUV masks have to be evaluated and fundamental material limits have to be overcome. We report on optimized absorber-stack materials and compare in particular the performance of chrome and tantalum nitride for such small nodes. Tantalum nitride shows similar or even better properties than standard chrome, above all with respect to etch bias. Further investigations have to be done but this material is a promising candidate for feature sizes in the sub-50 nm range.