We present a new method of sidelobe suppressor placement based on fast lithographic simulation. Experimental results of printing 0.18 micron contact holes using a 5.5 percent transmittance attenuated phase shift mask with different settings of partial coherency are shown. Very asymmetric side lobes appear in some of these results. To explain these experimental results simulations were performed that take koma lens aberrations into account. A good agreement between experiment and simulation can be obtained them, Using these simulations a new algorithm has been implemented to place absorbing assist pattern for sidelobe suppression suitable in size and position. Then the process window of a double contact was determined using aerial image simulation. Process windows with koma lens aberrations and different settings of the partial coherency are then compared.
The reduction of the wave length in the optical lithography in combination with mask enhancement techniques like phase shift pattern, optical proximity correction (OPC) or off- axis illumination requires a rapid increase in measurement accuracy and cost effective qualification of advanced photo masks. The knowledge about the impact of CD deviations, loss of pattern fidelity--especially of OPC structures--and mask defects on wafer level in more and more essential for mask qualification.
The paper describes the extension of optical proximity correction (OPC), which is well established for conventional chromium-on-glass mask printing, to alternating phase shift masks (altPSM). Aerial image simulation of various situations of light-field and dark-field altPSM shows that the size of the phase shifter has a great impact on the printed critical dimension (CD). Especially layouts containing non-symmetric phase shifters or shifter sizes comparable to the nominal CD do not print on target. The application of optical proximity correction to the chromium structures between the phase shifters is capable to compensate for such effects. We demonstrate the added value of OPC using a simulation-based software tool for altPSM.
The pattern transfer process from the chip layout data to the structures on the finished wafer consists of many process steps. Although desired, none of these steps is linear in all aspects of the pattern transfer. Approaching the process limits due to the ever-shrinking linewidth, the non- linearities of the pattern transfer clearly show up. This means, that one cannot continue the practice to summarize all process influences into one bias between the data used for mask making and the final chip structure. The correction of process non-linearities is a necessity. This correction is usually called optical proximity correction (OPC), although not all effects intended for correction are of optical origin and/or not all these are effects of the neighborhood. We therefore propose to use the term PPC (process proximity correction). This paper reports our experiences with the application of OPTISSIMO, a software tool developed to perform automatically OPC/PPC for full chip designs. First, we provide a definition of PPC, which in our view has to correct all non- linearities of the pattern transfer process from layout data to the final electrically measured structures. Then, the strategy of the OPC/PPC tool OPTISSIMO, a software package to perform PPC based on process simulation, is discussed. We focus on the data handling strategy and on the process modeling of the tool under evaluation. It is shown, that full chip OPC/PPC is practicable using a well-designed hierarchy management system combined with a pattern library. Finally, it is demonstrated, that a model-based OPC/PPC tool is by definition a process simulation tool, that is able to perform all simulation tasks (like defect printability) at reasonable accuracy.
The implementation of a simple, semi-empirical resist model into an OPC algorithm, which up to now uses aerial image simulation, is described. The model assumes that the main component of proximity effects comes from the aerial image. It uses two pattern density functions to describe the shift in edge placement due to resist and etching processes. Besides the parameters for the aerial image (numerical aperture, coherence, wavelength, lens aberrations, defocus, etc.), the model needs only four additional parameters. The model is tested using resist simulation and electrical linewidth measurement data from fully processed testwafers. For linewidths of 350 nm and larger, printed with i-line lithography into a standard i-line resist, the OPC algorithm with the implemented model reduces proximity effects to less than 10 nm. A similar performance is indicated by preliminary data of electrical linewidth measurements.
One of the most prominent process non-linearities, which are summarized under 'proximity effects' is line-shortening. Line- shortening is poorly modeled by phenomenological lithography simulation -- even when resist models are used, which deliver reasonable results for process windows and resist edge profiles. So the challenge for a simulation-based OPC tool is not only the required speed, but also a lack in thoroughly understanding the processes involved. The OPC tool OPTISSIMO describes optical pattern transfer primarily by simulation of the aerial image according to a phenomenological model. Differences from the actual measured dimensions (either after resist processing or after etching) are described as corrections to the aerial image simulation results. These corrections are fitted by an empirical model. We show in this paper, that this model is not only able to explain the linewidth changes due to proximity effects, but also to describe line-shortening effects with reasonable accuracy. Further we show, that using a 'hammerhead design approach' (a rectangle placed over the end of each line) is a very effective way to compensate line-shortening This technique does not require an increase of resolution at mask fabrication and increases the data volume of the corrected design only moderately. Therefore, the addition of hammerheads to the line-mode of OPTISSIMO is a very promising method to perform OPC at full-chip designs and with available mask manufacturing techniques.