Line edge roughness (LER) reduction is critical during the patterning process definition and development, as the critical dimension (CD) and pitch scale in advanced semiconductor technology nodes. In this paper, we will focus on a 7nm self-aligned double patterning (SADP) process for use in back end of line (BEOL). Specifically, we will investigate LER from various lithography options and how LER changes through downstream processes, including mandrel etch, spacer deposition, hard mask open, dielectric etch and wet clean. We characterized LER as a function of several mandrel etch parameters such as O2 flow rate, over etch rate percentage and polymer deposition rates. We also characterized LER response to dielectric etch parameters and found that while some etch processes may smooth high frequency LER, there are additional cases where the final etch and wet-clean increased LER and line wiggling. Overall, we observed that lithography is the primary source of LER and we have the opportunity to reduce LER by both design and process optimization. In this paper we focused on characterization of a standard logic cell with varied CD and pitch. We looked through various designs, retargeting as well as both negative tone developer (NTD) and positive tone developer (PTD) resists for the LER reduction. We also analyzed the image log slope (ILS) of each corresponding edge and the process windows of the resist candidates. We concluded that ILS improvement and resist selection are the primary knobs to reduce LER. With optimization, we can achieve LER close to the process assumption targets for 7nm technology node. Further LER reduction techniques are definitely needed in both 7nm and future nodes even with migration from 193nm to EUV lithography.
It is challenging to develop 45nm node contact hole using dry ArF lithography process with acceptable lithographic margin due to small process window and large mask error enhancement factor (MEEF). No single process using conventional lithography without resolution enhancement technique (RET) application will meet DOF requirement of 45nm node contact hole. We have developed dry ArF lithography processes for 45nm node contact hole on scanner ASML XT1400E by applying RETs including off-axis illumination, SAFIER (Shrink Assist Film for Enhanced Resolution) process, EFESE (focus scan), etc.
The paper will discuss process window through pitches with optimized illumination, and where to separate pitches in case of double exposure with consideration of DOF and OPC model simulation. It will look into the effect of EFESE on DOF improvement, proximity, and MEEF at various pitches. The paper will also discuss OPC modeling strategy for 45nm node contact/via hole. It will analyze the effect of OPC grid size on OPC run time, file size, and edge placement error (EPE).
To extend process further to 32nm node, we demonstrated the process capability for 32nm node hole using double patterning technique. We achieved 50nm final hole CD with pitch of 100nm. A hard mask (HM) technique was implemented in the process. The dense feature is designed into two complementary parts on two masks such that the density is reduced by half and minimum pitch is increased by at least a factor of 2<sup>1/2</sup> depending on design. The complete patters are formed with two litho-etch process steps. After the first mask litho process, the HM is etched. Then the second mask litho process is carried out and followed by a second HM etch and main etch.