The recent explosive compute growth, mainly fueled by the boost of artificial intelligence (AI) and deep neural networks (DNNs), is currently instigating the demand for a novel computing paradigm that can overcome the insurmountable barriers imposed by conventional electronic computing architectures. Photonic neural networks (PNNs) implemented on silicon photonic integration platforms stand out as a promising candidate to endow neural network (NN) hardware, offering the potential for energy efficient and ultra-fast computations through the utilization of the unique primitives of light i.e. THz bandwidth, low-power and low-latency. Thus far, several demonstrations have revealed the huge potential of PNNs in performing both linear and non-linear NN operations at unparalleled speed and energy consumption metrics. Transforming this potential into a tangible reality for Deep Learning (DL) applications requires, however, a deep understanding of the basic PNN principles, requirements and challenges across all constituent architectural, technological and training aspects. In this paper we review the state-of-the-art photonic linear processors and project their challenges and solutions for future photonic-assisted machine learning engines. Additionally, recent experimental results using SiGe EAMs in a Xbar layout are presented, validating light's credentials to perform ultra-fast linear operations with unparalleled accuracy. Finally, we provide an holistic overview of the optics-informed NN training framework that incorporates the physical properties of photonic building blocks into the training process in order to improve the NN classification accuracy and effectively elevate neuromorphic photonic hardware into high-performance DL computational settings.
Photonic Neural Networks (PNNs) implemented on silicon photonic (SiPho) platforms stand out as a promising candidate to endow neural network hardware, offering the potential for energy efficient and ultra-fast computations through exploiting the unique primitives of light i.e., THz bandwidth, low-power and low-latency. In this paper, we review the state-of-the-art photonic linear processors discuss their challenges and propose solutions for future photonic-assisted machine learning engines. Additionally, we will present experimental results on the recently introduced SiPho 4x4 coherent crossbar (Xbar) architecture, that migrates from existing Singular Value Decomposition (SVD)-based schemes while offering single time-step programming complexity. The Xbar architecture utilizes silicon germanium (SiGe) Electro-Absorption Modulators (EAMs) as its computing cells and Thermo-Optic (TO) Phase Shifters (PS) for providing the sign information at every weight matrix node. Towards experimentally evaluating our Xbar architecture, we performed 10,024 arbitrary linear transformations over the SiPho processor, with the respective fidelity values converging to 100%. Followingly, we focus on the execution of the non-linear part of the NN by demonstrating a programmable analog optoelectronic circuit that can be configured to provide a plethora of non-linear activation functions, including tanh, sigmoid, ReLU and inverted ReLU at 2 GHz update rate. Finally, we provide a holistic overview on optics-informed neural networks towards improving the classification accuracy and performance of optics-specific Deep Learning (DL) computational tasks by leveraging the synergy of optical physics and DL.
Rapid developments in computer science have led to the increasing demand for efficient computing systems. Linear photonic systems rose as a favorable candidate for workload-demanding architectures, due to their small footprint and low energy consumption. Mach Zehnder Interferometers (MZI) serve as the foundational building block for several photonic circuits, and have been widely used as modulators, switches and variable power splitters. However, combining MZIs for realizing multiport splitters remains a challenge, since the exponential increase in the number of devices and the consequential increase in losses is limiting the performance of the MZI based multiport device. To overcome such limitations, incorporating alternative and low loss integration platforms combined with a generalized design of the MZI could allow the realization of a robust variable power splitter. In this work, we present for the first time a 4×4 Generalized Mach Zehnder Interferometer (GMZI) incorporated on a Si3N4 photonic integration platform and we experimentally demonstrate its operation as a variable power splitter. We developed an analytical model to describe the operation of the 4×4 GMZI, allowing us to evaluate the impact of several parameters to the overall performance of the device and investigate the device’s tolerance to fabrication imperfections and design alternations. Its experimental evaluation as a variable power splitter reveals a controlled imbalance that ranges up to 10 dB in multiple output ports of the device, validating the theoretically derived principles of operation.
During the past years, the processor-memory performance gap, also known as “Memory Wall” problem, has forced designers to allocate more than 50% of the chip real-estate for caching purposes to alleviate limited memory bandwidth. Optical technology holds the credentials of delivering high-bandwidth and energy-efficient photonic integrated memories that could revisit the traditional computing architectures. The migration, however, to fully functional and practical optical RAMs will require the exploitation of wavelength dimension as well as seamless cooperation between storage and peripheral decoding units, for efficient RAM architectural layouts. In this paper we present the first demonstration of an all-optical 8-bit RAM storage unit comprising WDM-enabled 2×4 Row and 1×4 Column Decoders and a 2×4-bit optical RAM Bank for storing a 20Gb/s 4-bit WDM-formatted optical data word per row. The proposed scheme incorporates a shared multi-λ SOA-MZI Access Gate (AG) per Word Line (WL) for granting access-control to the appropriate word line, WL “00” or WL “01”, and a passive Column Decoder that directs the incoming WDM-formatted data words to the respective RAM cells. Each RAM cell is in turn based on an elementary monolithically integrated InP photonic Flip-Flop (FF). The proposed architecture is experimentally verified for successful Write operation of a 4-bit WDM word to a selected 4-bit RAM row at 20Gb/s RAM throughput and a peak power penalty within the range of [7.8-10.7] dB, promising a 4× speed-up in memory-access throughput and paving the way for high-bandwidth multi-bit optical RAM-architectures that may relax the memory-bottleneck of computing architectures.
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