A post-CMOS process for chip-level monolithic integration has been developed. A metal probe array for recording neural signals is utilized as a test vehicle to realize the integration process. This probe array is fabricated on a 2 mm x 2 mm chip containing eight ultra-low power CMOS operational amplifiers. A LIGA-like process is employed utilizing UV lithography on SU-8 photoresist and pulse electroplating technique. Pulse plating significantly reduces stress in the deposited material. The post-CMOS fabrication process is utilized to fabricate 70 μm high probes having different aspect-ratios that are monolithically integrated on the CMOS chip.
A microprobe array for recording neural signals has been designed and fabricated for future monolithic integration with an ultra-low power CMOS operational amplifier circuit on a 2 mm × 2 mm chip. A LIGA-like process is employed utilizing UV lithography and electrodeposition techniques. Probes are fabricated on silicon substrate. The fabrication process is compatible with monolithic integration with CMOS signal processing circuitry. The probes are 210 um high and have an aspect ratio 3:1. Comments are made on processing issues related to chip-level monolithic integration.
A CMOS analog multiplexer circuit has been designed for operation at 0.8 V. The circuit consists of transmission gates as switches and an inverter. MOSFETs in the design of multiplexer use the dynamic body bias method. The forward body bias is limited to no more than 0.4 V to avoid CMOS latch-up. The reverse body bias is limited to 0.4 V and allows the MOSFET to turn-off fully and suppresses the sub-threshold leakage. The improved dynamic threshold MOSFET (DTMOS) inverter is engaged to achieve low voltage operation. The CMOS multiplexer chip was designed in standard 1.5 μm n-well CMOS technology and simulated using SPICE. Excellent agreement was obtained between the simulated output waveform and corresponding experimentally measured behavior. The power dissipation is close to 70 nW and signal-to-leakage ratio is 120 dB. The proposed low voltage, ultra-low power analog multiplexer would find application for on-chip neural microprobes and other applications.
A CMOS test chip has been designed and fabricated which can monolithically integrate ultra low-power operational amplifiers with neural microprobes through post-IC processing. Neural microprobes of varying widths (70 μm, 60 μm, 50 μm, and 40 μm) are designed with varying center-to-center spacing (195 μm, 175 μm, 165 μm, 155 μm, 145 μm, and 125 μm) on a test chip for integration. Neural microprobes are first fabricated on a separate Si substrate to develop a fabrication process for post-IC processing for integration. The amplifier is designed in standard 1.5 μm CMOS process for operation at ∓ 0.4 V. Low power performance is realized by combining forward biased source-substrate junction MOSFETs with a novel low-voltage level-shift current mirror. The designed amplifier gives a gain of 7000 (77 dB) and a 3-dB bandwidth of 30 kHz. The amplifier output has a positive offset of only 20 μV and power dissipation of only 40 μW.
Noise due to back-gate forward bias between substrate and source of a MOSFET is analyzed and simulated. Noise level is compared between two CMOS circuits with and without back-gate forward bias. It is found that the output noise introduced by the back-gate forward bias method is only a few nV/square root (Hz), which only slightly increases the device noise. A CMOS op-amp is designed utilizing back-gate forward bias technique utilizing a level shift current mirror for operation at ultra low-power in μW range. The designed amplifier dissipates power of 40 uW and operates at ± 0.4 V to achieve a gain of 77 dB. The noise in ultra low-power op-amp is also investigated. The total output noise density is about 30 μV/square root (Hz) in the ultra-low power op-amp design, which is lower than 65 μV/square root (Hz) of standard op-amp. The signal to noise ratio of the ultra low-power op-amp is 44 dB.