Detection of resist residue and organic contamination after photo resist strip and wafer clean early in the high K/metal
gate (HK/MG) manufacturing process flow is critical as it has been known to significantly impact yield. This residue,
when exposed to subsequent thermal process steps, transforms into solid hard spot(s), and can then be detected by a
wafer inspection tool, but unfortunately it is too late to take corrective action. A unique process control solution to detect
the presence of residues was developed using advanced analysis of an optical scattering inspection of a litho checkerboard pattern. The presence of residue was then validated with film thickness measurements.
The present practice of managing reticle haze defectivity involves reticle inspection at regular intervals, coupled with
inspection of print-down wafers in between reticle inspections. The sensitivity of the reticle inspection tool allows it to
detect haze defects before they are large enough to print on the wafer. Cleaning the reticle as soon as the reticle inspector
detects haze defects could result in a shorter reticle lifetime. Thus there is strong motivation to develop a methodology to
determine what size defect on the reticle results in a printable defect on the wafer. Printability depends upon several
variables in the litho process as well as whether the defect resides in a high-MEEF (Mask Error Enhancement Factor) or
low-MEEF area of the die.1 Trying to use wafer inspection to identify the first appearance of haze defects may require
inspector recipe settings that are not suited to a practical wafer scan.
A novel method of managing such defects is to map the coordinates of the defects from the reticle onto the wafer, and
apply a separate, hyper-sensitive threshold to a small area surrounding the given coordinates. With this method, one can
start to correlate the size of the defects printed on the wafer to the light transmission rate from the corresponding site on
the reticle scan, and thus can predict the starting point at which the haze defects on the reticle are likely to print on the
wafer. The experiment described in this paper is a first step in exploring the feasibility of this method to help track the
growth of nascent haze defects and optimize the timing to rework the reticles. The methodology may have extendibility
to other applications in which hyper-sensitive wafer inspection at localized areas within the die would be beneficial, such
as monitoring weak spots found by Optical Rule Check, Process Window Qualification, electrical test or failure analysis.
Identifying hotspots--structures that limit the lithography process window--become increasingly important as the
industry relies heavily on RET to print sub-wavelength designs. KLA-Tencor's patented Process Window Qualification
(PWQ) methodology has been used for this purpose in various fabs. PWQ methodology has three key advantages (a)
PWQ Layout--to obtain the best sensitivity (b) Design Based Binning--for pattern repeater analysis (c) Intelligent
sampling--for the best DOI sampling rate. This paper evaluates two different analysis strategies for SEM review
sampling successfully deployed at Inotera Memories, Inc. We propose a new approach combining the location repeater
and pattern repeaters. Based on a recent case study the new sampling flow reduces the data analysis and sampling time
from 6 hours to 1.5 hour maintaining maximum DOI sample rate.
In the early development stage of 32nm processes, identifying and isolating systematic defects
is critical to understanding the issues related to design and process interactions. Conventional
inspection methodologies using random review sampling on large defect populations do not provide
the information required to take accurate and quick corrective action. This paper demonstrates the
successful identification and isolation of systematic defects using a novel methodology that
combines Design Based Binning (DBB) and inline Defect Organizer (iDO). This new method of
integrating design and defect data produced actionable inspection data, resulting in fewer mask
revisions and reduced device development time.