As lithography moves into lower k1 imaging, traditional illumination "source" shapes may perform
marginally in resolving complex layouts. Subsequently hot-spots or warm-spots can result, leading to yield
loss in production. Typically, lithographers solve such problems by modifying the local layout instead of
optimizing the DOE (diffractive optical element) illumination shape. FlexRayTM can easily implement
freeform source shapes and allows a high degree of freedom in source optimization. Therefore, it becomes
practical to use pixelated freeform sources to resolve hot spots or warm spots.
In this paper, we investigate the use of freeform source optimization (SO) on a critical dynamic random
access memory (DRAM) layer with warm spots to verify the effectiveness of a SO only flow using
Tachyon SMO. In order to improve the warm spots without changing baseline performance for other
patterns, we optimized not only the warm spot patterns of concern but also the critical reference patterns.
Since the optimization minimizes EPE (edge placement error) and maximizes imaging quality for all
enclosed patterns, the final optimized source shape performs similar to the baseline source for the base
patterns while improving the performance of the warm spot pattern areas. Although the SO source is
similar in shape to the baseline source, the optimized source provides enhanced depth of focus (DoF) for all
warm spot patterns without suffering degradation in the normalized image log-slope (NILS) performance.
Evaluation of the optimized SO source shows no obvious negative impact on modeled CDs across an array
of L/S pattern combinations which cover all the pitches appearing in the periphery. Finally, the optimized
source is demonstrated using ASML's FlexRayTM for on-wafer evaluation. According to the observations
from on-wafer experiments, consistent results to simulation are verified. Overall DoF for the identified
warm spot patterns is definitely improved and no obvious pattern shape changes are found, as well.
From the positive demonstration in simulation and on-wafer verification, the vast flexibility of the freeform
source enables the SO flow with more powerful capability to improve local hot spot or warm spot problems
without negatively impacting the other patterns.
Given the continually decreasing k1 factor and process latitude in advanced technology nodes, it is important to fully
understand and control the variables that impact imaging behavior in the lithography process. In this joint work between
TSMC and ASML, we use model-based simulations to characterize and predict the imaging effects of these variables
and to fine-tune the scanner settings based on such information in order to achieve optimal printing results on a perreticle
basis. The scanner modeling makes use of detailed scanner characteristics as well as wafer CD measurements for
accurate model construction. Simulations based on the calibrated model are subsequently used to predict the wafer
impact of changes in tunable scanner parameters for all critical patterns in the product. The critical patterns can be
identified beforehand, either experimentally on wafer, mask or through model simulations. A set of optimized scanner
setting offsets, known as a "scanner tuning recipe" is generated to improve the imaging behavior for the critical patterns.
We have demonstrated the efficacy of this methodology for multiple-use cases with selected ASML scanners and TSMC
processes and will share the achieved improvements on defect reduction and yield improvements.
Given the decrease in k1 factor for 65nm-node lithography technology and beyond, it is increasingly important to
understand and control the variables which impact scanner imaging behavior in the lithography process. In this work, we
explore using model simulations to characterize and predict imaging effects of these variables, and then based on such
information to fine-tune the scanner settings to obtain printing results optimally matched to a reference scanner. The
scanner modeling makes use of detailed scanner characteristics as well as wafer CD measurements for accurate model
construction. To identify critically mismatched patterns on a production layout, we employ the fast full-chip simulation
capability provided by Brion's Tachyon servers. Tachyon simulations are also used to predict wafer impacts of changes
in tunable scanner parameters. A set of optimized scanner variable offsets, called a "scanner tuning recipe", is generated
to minimize overall imaging mismatch between two scanners. As a proof-of-concept, we have carried out scanner tuning
procedures on selected ASML scanners. The results show improvements more than 20% on CD offset RMS values for
2D line-end patterns, production layout patterns, and the mismatched patterns identified with the full-chip simulation.
Improvements on wafer-acceptance-test results and production yield on the to-be-tuned scanner are also observed.
Resolving the very small feature size of contact holes for 65-nm technology node has placed enormous challenge on even the up-to-date optical lithography techniques. Resolution enhancement technique (RET) will be helpful and necessary to alleviate the strain posed by such a task. Here we report that a 193-nm alternating phase shift mask (Alt-PSM) with phase-shifted assist features is used to print the contact holes for 65-nm node. With a novel algorithm of phase assignment, the phases of the main features are assigned properly in the full chip with the assistant features added. The results show that DOF of 110-nm iso-contact hole can be enhanced up to 0.5 μm.
In this paper, the simulation of wafer images for Alternating Aperture Phase Shift Masks is addressed by comparing wafer printing image with simulation. This is the first accuracy study for Virtual Stepper's newly developed AAPSM simulation module. The test reticle used includes 70 nm gate structures with three types of programmed phase defects: edge, corner, and center defects on rectangular shifter patterns. Wafer exposures are performed using 193 nm imaging technology and inspection images generated on a KLA-Tencor's SLF27 system. These images are used by the Virtual Stepper System to provide simulated wafer images using the specified stepper parameters. The results are compared to the simulation results from the Aerial Image Measurement System (AIMSTM) and SEM images of resist patterns.
Double exposure alternating phase-shift mask (alt-PSM) technology with ArF exposure was used in the 0.1 micrometers technology node for patterning logic devices with polysilicon gates ranging from 110nm to 60nm. A dual-trench mask fabrication process was developed in-house at TSMC, and controls for phase accuracy and intensity balance were established. Optical proximity correction (OPC) was performed on both binary masks and alt-PSM. Interactions between the binary and the PSM exposures were taking in to accounted during the correction. Using Model based OPC and a single calibrated resist model, the critical dimensions (CD) linearity can be ideally matched to the designed CD for duty ratio >= 1:1.5 for polygate logic product has been implemented exhibiting an enlarged DOF, good resist line edge roughness (LER), a d CD uniformity.
The present study aims to evaluate the utilization of assisting features in the contact-hole mask repair. Several different types of assisting features were considered, including positive serifs, constant bias, assisting bars, and assisting dimples. In brief, a test mask was fabricated to render various extent of quartz damage using a focused- ion beam mask repair tool, followed by adding assisting features. The repaired contact holes were examined first by AIMS 193 (193 nm aerial image measurement system) for their optical transmission, critical dimension (CD), and exposure- defocus window (ED). Figure 1 and 2 illustrate some preliminary results acquired from AIMS 193. As revealed from Figure 2, the center of the exposure-defocus window is shifted by variant extend with adding different types of assisting features. Wafer printed results would be used to further verify AIMS 193 observation. Optical simulation results of these repaired holes with assistant features will also be presented using Solid C simulation tool.
Off-axis illumination (OAI) has been shown as one of the most practical resolution enhancement techniques (RET) available for optical lithography. A customized off-axis illumination aperture filter (CIF) was designed to gain the benefits of OAI and keep the optical proximity effect (OPE) in a manage-able range for sub-0.18micrometers line and space patterns. The performance of the filter comparing with conventional, annular and quadruple illuminations in term of depth of focus, OPE, throughput, dose and power uniformity for both 0.18micrometers and 0.15micrometers NA Nikon KrF excimer laser stepper with a maximum partial coherence factor of 0.8 is presented in the paper. A brief description of the design principle of the filter is also given. A summarized conclusion on the weakness of the filter and possible improvements is also presented in the paper.