Mr. Chungwei Michael Hsu Profile

Chungwei Michael Hsu

at ASML Taiwan Ltd

SPIE Involvement:

Author

Publications (36)

Proceedings Article | 23 March 2011 Paper

Improvement of lithography process by using a FlexRay illuminator for memory applications

Thomas Huang, Chun-Yen Huang, Tsann-Bim Chiou, Michael Hsu, Chiang-Lin Shih, Alek Chen, Ming-Kang Wei

Proceedings Volume 7973, 79731X (2011) https://doi.org/10.1117/12.879567

KEYWORDS: Source mask optimization, Optical proximity correction, Fiber optic illuminators, Diffractive optical elements, Semiconducting wafers, Scanners, Lithography, Manufacturing, Photomasks, Finite element methods

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As is well recognized, source mask optimization (SMO) is a highly effective means of extending the lifetime of a certain photolithography generation without an expensive upgrade to the next generation optical system. More than an academic theory, source optimization first found practical applications in the debut of the pixel-like programmable illuminator in 2009 for producing near freeform illumination. Based on programmed illumination, related studies have demonstrated a nearly identical optical performance to that generated by the conventionally adopted diffractive optical element (DOE) device without the prolonged manufacturing time and relatively high cost of stocking up various DOEs. By using a commercially available pixel-like programmable illuminator from ASML, i.e. the FlexRay, this study investigates the effectiveness of FlexRay in enhancing image contrast and common process window. Before wafer exposure, full SMO and source-only (SO) optimization are implemented by Tachyon SMO software to select the optimum illumination source. Wafer exposure is performed by ASML XT:1950i scanner equipped with a FlexRay illuminator on a critical layer of DRAM process with known hotspots of resist peeling. Pupil information is collected by a sensor embedded in the scanner to confirm the produced source shape against the programmed source and the optically simulated CD. When the FlexRay illuminator is used, experimental results indicate that lithography hotspots are eliminated and depth of focus is improved by as much as 50% in comparison with those from a traditional AERIAL illuminator. Regular focus-exposure matrix (FEM) and the subsequent critical defects scanning reveal that the common process window of the tight-pitched array and the periphery can be enhanced simultaneously with no hotspot identified. Therefore, a programmed source is undoubtedly invaluable in terms of additional manufacturing flexibility and lower cost of ownership when attempting to improve product yield in high volume production.

Proceedings Article | 7 March 2008 Paper

Manufacturing implementation of 32nm SRAM using ArF immersion with RET

Sho-Shen Lee, Cheng-Han Wu, Yongfa Huang, Chien-Hui Huang, Hung-Chin Huang, George KC Huang, Chun-Chi Yu, Michael Hsu, Simon Shieh, Stephen Hsu, T. B. Chiao

Proceedings Volume 6924, 69242X (2008) https://doi.org/10.1117/12.773137

KEYWORDS: Resolution enhancement technologies, Photomasks, Optical proximity correction, Semiconducting wafers, Manufacturing, Polarization, Electroluminescence, Printing, Critical dimension metrology, Metals

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Proceedings Article | 15 May 2007 Paper

Implementation of double dipole lithography for 45-nm node poly and diffusion layer manufacturing with 0.93NA

Meng-Hsiu Wu, Michael Hsu, Stephen Hsu, Bo-Jou Lu, Yung-Feng Cheng, Yueh-Lin Chou, Chuen-Huei Yang

Proceedings Volume 6607, 660731 (2007) https://doi.org/10.1117/12.729020

KEYWORDS: Photomasks, Critical dimension metrology, Optical proximity correction, Semiconducting wafers, Resolution enhancement technologies, Lithography, Manufacturing, Calibration, Data modeling, Printing

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The double dipole lithography (DDL) has been proven to be one of the resolution enhancement technologies for 45 nm node. In this paper, we have implemented a full-chip DDL process for 45nm node using ArF immersion lithography. Immersion exposure system can effectively enlarge the process DoF (depth of focus). Combining with dipole illumination can help us to reach smaller k1 value (~0.31) and meet the process requirements of poly and diffusion layers on 45nm node by using only 0.93 NA exposure tool. However, from a full-chip processing point of view, the more challenging question should be: how to calibrate a good model from two exposure and decompose original design to separate mask sets? Does the image performance achieve a production worthy standard? At 45nm node, we are using one-fourth of the exposure wavelength for the patterning; there is very little room for error. For DDL full-chip processing, we need a robust application strategy to ensure a very tight CD control. We implemented an integrated RET solution that combines DDL along with polarization, immersion system, and model based OPC to meet full-chip manufacturing requirement. This is to be a dual-exposure mask solution for 45nm node - X-dipole exposure for vertical mask and horizontal for Y-dipole. We show a process design flow starting from the design rule analysis, layout decomposition, model-based OPC, manufacturing reliability check, and then to the mask data preparation. All of the work has been implemented using MaskWeaver^TM geometry engine. Additionally, we investigated printability for through-pitch line features, ASIC logic, and SRAM cell design patterns. Different circuit layout needs dedicated special OPC treatment. To characterize the related process performance, we use mask enhancement error factor (MEEF), process window (PW), and critical dimension uniformity (CDU) to analyze the simulation data. Since we used the tri-tone Att-PSM, the mask making flow and spec was also taking into consideration. The device electrical performance was examined for production feasibility. We conclude that the DDL process is ready for 45nm node and is well within reach to be used on next generation production environment.

Proceedings Article | 4 April 2007 Paper

Quantification of two-dimensional structures generalized for OPC model verification

Xuelong Shi, J. Fung Chen, Doug Van Den Broeke, Stephen Hsu, Michael Hsu

Proceedings Volume 6518, 65180A (2007) https://doi.org/10.1117/12.713867

KEYWORDS: Calibration, Optical proximity correction, Data modeling, Photomasks, Imaging systems, Mathematical modeling, Design for manufacturing, Statistical modeling, Lithography, Image processing

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Model based optical proximity correction (OPC) today has become a necessity in advanced lithography for 65nm and 45nm design rules in order to achieve production-worthy pattern fidelity. The typical practice is to use a limited set of test structures to calibrate and determine the OPC model parameters. The guide for the selection of test structures for OPC model calibration has been mainly relied on experience and physical intuition. To date, there is no known quantification methodology to ensure that the calibrated model from a limited set of test structures can reliably "cover" a full-chip OPC application without any ambiguity under a known set of design rule constraints. Doubts from this ambiguity demand an extra design for manufacturing (DFM) verification step in addition to the already lengthy OPC application process. This is since semiconductor manufacturing requires that the post-OPC mask data contains no errors, or at least no catastrophic errors induced by OPC treatment, e.g., bridging or short. However, such DFM verification tools are again based on a perilous assumption that either one can use the same or yet another "calibrated" model from a limited set of test structures to check the OPC treated full-chip data for all possible trouble spots. In reality, a "calibrated" model may never be able to apply adequately to those of random two-dimensional (2-D) pattern structures on a full-chip that are lithographically unrelated to the limited set of test structures used for the model calibration. To ensure a more comprehensive coverage of the OPC model, we need a methodology that can quantify generalized 2-D test structures suitable for model calibration. In this paper, we propose a method to quantify generalized, 2-D patterns by representing them in "imaging signal space". The method that translates geometrical design rules into the boundary in "imaging signal space" is elaborated. We propose several critical quantities to characterize OPC model on a quantitative foundation to assess model from a statistical point of view.

Proceedings Article | 20 May 2006 Paper

RET masks for patterning 45nm node contact hole using ArF immersion lithography

Michael Hsu, J. Fung Chen, Doug Van Den Broeke, Shih En Tszng, Jason Shieh, Stephen Hsu, Xuelong Shi

Proceedings Volume 6283, 628317 (2006) https://doi.org/10.1117/12.681868

KEYWORDS: Photomasks, Resolution enhancement technologies, Printing, Etching, Optical proximity correction, Optical lithography, Imaging systems, Mask making, Quartz, Semiconducting wafers

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Immersion exposure system with the numerical aperture (NA) greater than unity effectively extends the printing resolution limit without the need of shrinking the exposure wavelength. From the perspective of imaging contact hole mask, we are convinced that a mature ArF immersion exposure system will be able to meet 45nm node manufacturing requirement. However, from a full-chip mask data processing point of view, a more challenging question could be: how to ensure the intended RET mask to best achieve a production worthy solution? At 45nm, we are using one-fourth of the exposure wavelength for the patterning; there is very little room for error. For full-chip, especially for contact hole mask, we need a robust RET mask strategy to ensure sufficient CD control. A production-worthy RET mask technology should have good imaging performance with advanced exposure system; and, it should base on currently available mask blank material and be compatible with the existing mask making process. In this work, we propose a new type of contact hole RET masks that is capable of 45nm node full-chip manufacturing. Three types of potential RET masks are studied. The 1st type is the conventional 6% attenuated PSM (attPSM) with 0-phase Scattering Bars (SB). The 2nd type is to use CPL mask with both 0- and π-phase SB, and their relative placements are based on interference mapping lithography (IML) under optimized illumination. The 3rd type, here named as 6% CPL, can be thought of as a CPL mask type with 6% transmission on the background but with π-phase SB only. Of those three RET masks, 6% CPL mask has the best performance for printing 45nm contact and via masks. To implement 6% CPL for contact and via mask design, we study several critical process steps starting from the illumination optimization, model-based SB OPC, 3D mask effect, quartz etch depth optimization, side-lobe printability verification, and then to the mask making flow. Additionally, we investigate printability for through-pitch contact array, and random contact design. To characterize the printing performance, we use MEEF, and process window (PW) to analyze the simulation data. We conclude that the 45nm node contact hole imaging is well within reach using a mature ArF immersion exposure tool with a robust and well integrated RET mask scheme.

Proceedings Article | 20 May 2006 Paper

Manufacturing implementation of IML technology for 45 nm node contact masks

Douglas Van Den Broeke, Michael Hsu, J. Fung Chen, Stephen Hsu, Uwe Hollerbach, Tom Laidig

Proceedings Volume 6283, 62831C (2006) https://doi.org/10.1117/12.681811

KEYWORDS: Reticles, Printing, Resolution enhancement technologies, Manufacturing, Algorithm development, Photomasks, Scattering, Binary data, Optical lithography, Detection and tracking algorithms

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For advance semiconductor manufacturing, patterning contact and via mask layers continue to be major challenge. As a result, RET's beyond the current standard 6% attPSM technology are being pursued with a goal of reducing the k₁ for hole patterning to the range of 0.35 - 0.40. IML Technology has shown promising results as a possible solution which employs strong off axis illumination (OAI) to achieve the resolution for the dense pitch contacts and the use of sub-resolution scattering bars (SB) for the semi dense to isolated contacts. At the 45nm node, placing SB by simply applying a set of rules is not sufficient for deriving the correct assist feature placements for the entire range of pitches and for the complex, randomly placed contacts that occur in actual device patterns. IML Technology utilizes modeling to locate where SB should be placed and in the case of high transmission ternary PSM (HTPSM) and CPL, defines the phase of the SB relative to the contacts being imaged. To generate such reticle designs, highly complex interference maps are calculated and from this optical interference behavior, the reticle pattern is derived. Previously, the reticle pattern derived in such a manner was extremely complex raising a question as to how feasible such an approach would be in a manufacturing environment. New algorithms which simplify the mask pattern while maintaining the resolution enhancement capability of IML have been developed. The objective of this work is to demonstrate a manufacturing methodology that utilizes IML Technology and is capable of meeting the requirements for the 45nm node designs. We will explore the application of this method 6% attPSM and CPL reticle designs which containing contact patterns that are representative of production devices. To define the SB for what are effectively randomly placed contacts over a wide range of pitches from dense to isolated, IML Technology is used. This modeling algorithm is based on mapping out the interference that occurs at the image plane as a result of the proximity effects of the target contact pattern. This technique provides a model-based approach for placing all types of assist features on both clear field and dark field patterns for the purpose of enhancing the printing resolution of the target pattern and it can be applied to any reticle type including binary, attPSM, altPSM, ternary HTPSM, and CPL. By implementing newly developed algorithms, simplified reticle patterns are generated which maintain the optimum SB placements determined by the IML process.

Proceedings Article | 9 November 2005 Paper

Implementation of random contact hole design with CPL mask by using IML technology

Michael Hsu, Doug Van Den Broeke, Stephen Hsu, J. Fung Chen, Xuelong Shi, Noel Corcoran, Linda Yu

Proceedings Volume 5992, 599237 (2005) https://doi.org/10.1117/12.633286

KEYWORDS: Photomasks, Optical proximity correction, Semiconducting wafers, Model-based design, 3D modeling, Printing, Resolution enhancement technologies, Optical lithography, Lithographic illumination, Lithography

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Proceedings Article | 8 November 2005 Paper

Patterning optimization for 55nm design rule DRAM/flash memory using production-ready customized illuminations

Ting Chen, Doug Van Den Broeke, Stephen Hsu, Michael Hsu, Sangbong Park, Gabriel Berger, Tamer Coskun, Joep de Vocht, Fung Chen, Robert Socha, JungChul Park, Keith Gronlund

Proceedings Volume 5992, 599239 (2005) https://doi.org/10.1117/12.633465

KEYWORDS: Electroluminescence, Printing, Nanoimprint lithography, Lithographic illumination, Cerium, Fiber optic illuminators, Manufacturing, Optical proximity correction, Optical lithography, Photomasks

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Illumination optimization, often combined with optical proximity corrections (OPC) to the mask, is becoming one of the critical components for a production-worthy lithography process for 55nm-node DRAM/Flash memory devices and beyond. At low-k₁, e.g. k₁<0.31, both resolution and imaging contrast can be severely limited by the current imaging tools while using the standard illumination sources. Illumination optimization is a process where the source shape is varied, in both profile and intensity distribution, to achieve enhancement in the final image contrast as compared to using the non-optimized sources. The optimization can be done efficiently for repetitive patterns such as DRAM/Flash memory cores. However, illumination optimization often produces source shapes that are "free-form" like and they can be too complex to be directly applicable for production and lack the necessary radial and annular symmetries desirable for the diffractive optical element (DOE) based illumination systems in today's leading lithography tools. As a result, post-optimization rendering and verification of the optimized source shape are often necessary to meet the production-ready or manufacturability requirements and ensure optimal performance gains. In this work, we describe our approach to the illumination optimization for k₁<0.31 DRAM/Flash memory patterns, using an ASML XT:1400i at NA 0.93, where the all necessary manufacturability requirements are fully accounted for during the optimization. The imaging contrast in the resist is optimized in a reduced solution space constrained by the manufacturability requirements, which include minimum distance between poles, minimum opening pole angles, minimum ring width and minimum source filling factor in the sigma space. For additional performance gains, the intensity within the optimized source can vary in a gray-tone fashion (eight shades used in this work). Although this new optimization approach can sometimes produce closely spaced solutions as gauged by the NILS based metrics, we show that the optimal and production-ready source shape solution can be easily determined by comparing the best solutions to the "free-form" solution and more importantly, by their respective imaging fidelity and process latitude ranking. Imaging fidelity and process latitude simulations are performed to analyze the impact and sensitivity of the manufacturability requirements on pattern specific illumination optimizations using ASML XT:1400i and other latest imaging systems. Mask model based OPC (MOPC) is applied and optimized sequentially to ensure that the CD uniformity requirements are met.

Proceedings Article | 28 June 2005 Paper

Application of CPL mask for whole chip 65nm DRAM patterning

Orson Lin, Richard Hung, Booky Lee, Yuan-Hsun Wu, Makoto Kozuma, Chiang-Lin Shih, Jengping Lin, Michael Hsu, Stephen Hsu

Proceedings Volume 5853, (2005) https://doi.org/10.1117/12.617230

KEYWORDS: Photomasks, Semiconducting wafers, Electron beam lithography, Manufacturing, Resolution enhancement technologies, Etching, Data modeling, Quartz, Chromium, Coating

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Proceedings Article | 28 June 2005 Paper

Model-based scattering bars implementation for 65nm and 45nm nodes using IML technology

Michael Hsu, Doug Van Den Broeke, Tom Laidig, Kurt Wampler, Uwe Hollerbach, Robert Socha, J. Chen, Stephen Hsu, Xuelong Shi

Proceedings Volume 5853, (2005) https://doi.org/10.1117/12.617165

KEYWORDS: Photomasks, Optical proximity correction, Model-based design, Performance modeling, Manufacturing, Scattering, Lithography, Semiconducting wafers, Printing, Diffractive optical elements

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Scattering Bars (SB) OPC, together with optimized illumination, is no doubt one of the critical enablers for low k₁ lithography manufacturing. The manufacturing implementation of SB so far has been mainly based on rule-based approach. While this has been working well, a more effective model-based approach is much more desired lithographically for manufacturing at 65nm and 45nm nodes. This is necessary to ensure sufficient process margin using hyper NA for patterning random IC design. In our model-based SB (M-SB) OPC implementation, we have based on the patented IML Technology from ASML MaskTools. In this report, we use both dark field contact hole and clear field poly gate mask to demonstrate this implementation methodology. It is also quite applicable for dark field trench masks, such as local interconnect mask with damascene metal. For our full-chip implementation flow, the first step is to determine the critical design area and then to proceed with NA and illumination optimization. We show that, using LithoCruiser, we are able to select the best NA in combination with optimum illumination via a Diffraction Optical Element (DOE). The decision to use a custom DOE or one from the available DOE library from ASML can be made based on predicted process performance and cost effectiveness. With optimized illumination, it is now possible to construct an interference map for the full-chip mask pattern. Utilizing the interference map, M-SB OPC is generated. Next, model OPC can be applied with the presence of M-SB for the entire chip. It is important to note here, that from our experience, the model OPC must be calibrated with the presence of SB in order to achieve the desired accuracy. We report the full-chip processing benchmark using MaskWeaver to apply both M-SB and model OPC. For actual patterning performance, we have verified the full chip OPC treatment using SLiC, a DFM tool from Cadence. This implementation methodology can be applied to binary chrome mask, attenuated PSM, and CPL.

Proceedings Article | 28 June 2005 Paper

RET masks for the final frontier of optical lithography

J. Chen, Douglas van den Broeke, Stephen Hsu, Michael Hsu, Tom Laidig, Xuelong Shi, Ting Chen, Robert Socha, Uwe Hollerbach, Kurt Wampler, Jungchul Park, Sangbong Park, Keith Gronlund

Proceedings Volume 5853, (2005) https://doi.org/10.1117/12.617430

KEYWORDS: Photomasks, Printing, Optical proximity correction, Lithography, Resolution enhancement technologies, Optical lithography, Manufacturing, Calibration, Optics manufacturing, Model-based design

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With immersion and hyper numerical aperture (NA>1) optics apply to the ITRS 2003/4 roadmap scenario (Figure 1); it is very clear that the IC manufacturing has already stepped into the final frontier of optical lithography. Today’s advanced lithography for DRAM/Flash is operating at k₁ close to 0.3. The manufacturing for leading edge logic devices does not follow too far behind. Patterning at near theoretical lithography imaging limit (k₁=0.25) even with hyper NA optics, the attainable aerial image contrast is marginal at best for the critical feature. Thus, one of the key objectives for low k₁ lithography is to ensure the printing performance of critical features for manufacturing. Resolution enhancement technology (RET) mask in combination with hyper NA and illumination optimization is one primary candidate to enable lithography manufacturing at very low k₁ factor. The use of rule-based Scattering Bars (SB) for all types of phase-shifting masks has become the de facto OPC standard since 180nm node. Model-based SB OPC method derives from interference mapping lithography (IML) has shown impressive printing result for both clear (gate) and dark field (contact and via) mask types. There are four basic types of RET mask candidates for 65nm node, namely, alternating phase-shifting mask (altPSM), attenuated PSM (attPSM), chromeless phase lithography (CPL) PSM, and double dipole lithography (DDL) using binary chrome mask. The wafer printing performances from CPL and DDL have proven both are strong candidates for 45nm nodes. One concern for using RET masks to target 45 nm nodes is likely to be the scaling for SB dimension for 4X mask. To assist imaging effectively with high NA, SB cannot be too small in width. However, for SB to be larger than sub-resolution, they can easily cause unwanted SB printing. The other major concern is the unwanted side lobe printing. This may occur for semi-dense pitch ranges under high NA and strong off-axis-illumination (OAI). Looking ahead, for manufacturing at 45 nm and 32nm nodes, one challenge is to break through the so-called k₁ barrier (0.25). Multiple exposure schemes in conjunction with RET masks is our proposed solution

Proceedings Article | 28 June 2005 Paper

Feasibility study of double exposure lithography for 65nm and 45nm node

Stephen Hsu, Douglas Van Den Broeke, J. Chen, Jungchul Park, Michael Hsu

Proceedings Volume 5853, (2005) https://doi.org/10.1117/12.617451

KEYWORDS: Photomasks, Polarization, Printing, Lithography, Dysprosium, Reticles, Binary data, Semiconducting wafers, Manufacturing, Diffraction

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There are many challenges ahead to use ArF for printing 45nm node device. High numerical aperture (NA) exposure tool and double exposure technique (DET) are the promising methods to extend ArF lithography manufacturing to 45nm node at k₁ factor below 0.35. Scattering bars (SB) have already become indispensable as chipmakers move to production in low k₁ factor. The optimum SB width is approximately (0.20 to 0.25)*(λ/NA). When SB width becomes less than the exposure wavelength, the Kirchhoff scalar theory is no longer accurate. When the optical weight of the SB increases, they become more easily printable. In order to ensure more robust lithography, both foundry and IDM prefer to choose higher NA exposure tool to maintain higher k₁ (>0.35). The chipmaker is currently using 0.85 NA, ArF, scanners for 65nm development and early device qualification. With immersion, the NA can be greater than 1.0. Under such a hyper NA (>1) condition, SB scalability and optical weight control are becoming even more challenging. Double exposure methods using either ternary 6% attenuated PSM (AttPSM) for DDL, or applying CPL mask with DDL, are good imaging solutions that can go beyond 45nm node. Today DDL with binary chrome mask is capable of printing 65 nm device patterns. Transmission tuning combined with OAI can achieve best-known imaging contrast for low k₁ lithography. In this work, we investigate the use of DDL with 6% ternary AttPSM to target 45nm node features. SB scalability issue can be addressed in both schemes since the SB can be exposed away using the combined dose from double exposures. Dipole with linearly polarized light can significantly improve the image contrast. The key to take advantage of polarization is to convert the layout into the corresponding x y patterns. We have developed model-based layout conversion method to generate both 6% AttPSM that can consider polarization effect. In this study, we share our initial findings through simulation and to report the initial binary mask printing result of DDL with linearly polarization.

Proceedings Article | 12 May 2005 Paper

Lithography manufacturing implementation for 65 nm and 45 nm nodes with model-based scattering bars using IML technology

Michael Hsu, Doug Van Den Broeke, Tom Laidig, Kurt Wampler, Uwe Hollerbach, Robert Socha, J. Chen, Stephen Hsu, Xuelong Shi

Proceedings Volume 5754, (2005) https://doi.org/10.1117/12.598589

KEYWORDS: Photomasks, Optical proximity correction, Model-based design, Manufacturing, Lithography, Performance modeling, Scattering, Printing, Diffractive optical elements, Design for manufacturing

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Scattering Bars (SB) OPC, together with optimized illumination, is no doubt one of the critical enablers for low k₁lithography manufacturing. ⁽¹⁾ The manufacturing implementation of SB so far has been mainly based on rule-based approach. While thiis has been working well, a more effective model-based approach is much more desired lithographically for manufacturing at 65nm and 45nm nodes. This is necessary to ensure sufficient process margin using hyper NA for patterning random IC design. In our model-based SB (M-SB) OPC implementation, we have based on the patented IML. Technology from ASML MaskTools.^(2,3) In this report, we use both dark field contact hole and clear field poly gate mask to demonstrate this implementation methodology. It is also quite applicable for dark field trench masks, such as local interconnect mask with damascene metal. For our full-chip implementation flow, the first step is to determine the critical design area and then to proceed with NA and illumination optimization. We show that, using LithoCruiser, we are able to select the best NA in combination with optimum illumination via a Diffraction Optical Element (DOE). The decision to use a custom DOE or one from the available DOE library from ASML can be made based on predicted process performance and cost effectiveness. With optimized illumination, it is now possible for MaskWeaver to construct an interference map for the full-chip mask pattern. Utilizing the interference map, M-SB OPC is generated. Next, model OPC can be applied with the presence of M-SB for the entire chip. It is important to note here, that from our experience, the model OPC must be calibrated with the presence of SB in order to achieve the desired accuracy. We report the full-chip processing benchmark using MaskWeaver to apply both M-SB and model OPC. For actual patterning performance, we have verified the full chip OPC treatment using SLiC, a DFM tool from Cadence. This implementation methodology can be applied to binary chrome mask, attenuated PSM, and CPL.

Proceedings Article | 27 January 2005 Paper

Improving the performance of E-beam 2nd writing in mask alignment accuracy and pattern faultless for CPL technology

Booky Lee, Richard Hung, Orson Lin, Yuan-Hsun Wu, Makoto Kozuma, Chiang-Lin Shih, Michael Hsu, Stephen Hsu

Proceedings Volume 5645, (2005) https://doi.org/10.1117/12.576542

KEYWORDS: Photomasks, Etching, Neodymium, Coating, Quartz, Chromium, Optical alignment, Scanning electron microscopy, Contamination, Image processing

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Proceedings Article | 6 December 2004 Paper

Double dipole lithography for 65-nm node and beyond: defect sensitivity characterization and reticle inspection

Stephen Hsu, Tsann-bin Chu, Douglas Van Den Broeke, J. Fung Chen, Michael Hsu, Noel Corcoran, William Volk, Wayne Ruch, Jean-Paul Sier, Carl Hess, Benjamin Lin, Chun-Chi Yu, George Huang

Proceedings Volume 5567, (2004) https://doi.org/10.1117/12.569367

KEYWORDS: Inspection, Reticles, Photomasks, Lithography, Resolution enhancement technologies, Defect inspection, Semiconducting wafers, Model-based design, Optical proximity correction, Scattering

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Proceedings Article | 6 December 2004 Paper

OPC model calibration for CPL patterning at extreme low k1

Xuelong Shi, Tom Laidig, J. Fung Chen, Douglas Van Den Broeke, Stephen Hsu, Michael Hsu, Kurt Wampler, Uwe Hollerbach, Jung Chul Park, Linda Yu

Proceedings Volume 5567, (2004) https://doi.org/10.1117/12.569655

KEYWORDS: Calibration, Optical proximity correction, Photomasks, 3D modeling, Mathematical modeling, Imaging systems, Image processing, Lithography, Scanning electron microscopy, Critical dimension metrology

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Proceedings Article | 6 December 2004 Paper

Full-chip manufacturing reliability check and correction (MRC2): a first step toward design for manufacturability with low k1 lithography

Michael Hsu, Tom Laidig, Kurt Wampler, Stephen Hsu, Xuelong Shi, J. Fung Chen, Douglas Van Den Broeke

Proceedings Volume 5567, (2004) https://doi.org/10.1117/12.568670

KEYWORDS: Photomasks, Manufacturing, Critical dimension metrology, Resolution enhancement technologies, Printing, Computer aided design, Lithography, Semiconducting wafers, Design for manufacturing, Reliability

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Proceedings Article | 20 August 2004 Paper

Full-chip manufacturing reliability check implementation for 90-nm and 65-nm nodes using CPL and DDL

Michael Hsu, Thomas Laidig, Kurt Wampler, Stephen Hsu, Xuelong Shi, J. Fung Chen, Douglas Van Den Broeke, Frank Hsieh

Proceedings Volume 5446, (2004) https://doi.org/10.1117/12.557792

KEYWORDS: Photomasks, Manufacturing, Optical proximity correction, Semiconducting wafers, Printing, Critical dimension metrology, Computer aided design, Reliability, Mask making, Resolution enhancement technologies

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Advanced masks such as CPL and DDL are the two leading low k1 lithography enablers for the upcoming 90nm and 65nm nodes. The mask generation methodologies for both have been clearly defined with convincing wafer printing results. We found that full-chip optical proximity correction (OPC) is by all means one of most critical components for CPL and DDL. The OPC process ensures the correct 2D pattern shapes and to achieve the desired CD to be printed on wafer with sufficient process margin. However, in addition to the already complex mask data generation, the OPC process further increases mask data complexity and more prone to data handling errors. It is therefore highly desirable to perform full-chip Manufacturing Reliability Check (MRC) prior to mask making. From our viewpoints, MRC needs to cover two goals: first is to single out the “weak printing spots” or to map out the treated CPL/DDL features with unacceptable DOF and exposure latitude so that the corrective actions can be taken, and second is to ensure printing of the entire chip to meet the process requirement. The success of MRC process depends on a well-trained modeling algorithm, which should be well capable of predicting the optical and resist behavior correctly across the entire chip. To perform a production worthy MRC for CPL (with two mask writing steps) and DDL (with two exposure masks), one must have a full knowledge of the mask generation principles for both. In this paper, we demonstrate a working scheme that has been designed to capture a variety of geometric variations on the treated mask layout that could lead to unacceptable printing performance. In this scheme, the MRC for CPL and DDL are handled in two separate modules and the final MRC data is characterized and classified into specified category. The predicted error points were reported and displayed through statistical analysis. Process tolerance during mask making was also taking into consideration. For the optimum MRC performance, we try to balance the wafer pattern fidelity, data complexity, and the mask cost. The fix suggestions for the failure discovered can be automatically proposed for some of specified layouts. This MRC method could also be applied to all types of PSM or multi-exposure mask.

Proceedings Article | 20 August 2004 Paper

Eigen-decomposition-based models for model OPC

Xuelong Shi, Thomas Laidig, J. Fung Chen, Douglas Van Den Broeke, Stephen Hsu, Michael Hsu, Kurt Wampler, Uwe Hollerbach

Proceedings Volume 5446, (2004) https://doi.org/10.1117/12.557794

KEYWORDS: Calibration, Optical proximity correction, Mathematical modeling, Lithography, Photomasks, Data modeling, Scanning electron microscopy, Image processing, Critical dimension metrology, Binary data

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Proceedings Article | 28 May 2004 Paper

RET integration of CPL technology for random logic

Stephen Hsu, Douglas Van Den Broeke, J. Fung Chen, Xuelong Shi, Michael Hsu, Thomas Laidig, Will Conley, Lloyd Litt, Wei Wu

Proceedings Volume 5377, (2004) https://doi.org/10.1117/12.537414

KEYWORDS: Photomasks, Nanoimprint lithography, Image transmission, Manufacturing, Optical proximity correction, Diffraction, Transmittance, Resolution enhancement technologies, Semiconducting wafers, Phase shifts

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Proceedings Article | 17 December 2003 Paper

Study of dry etching pattern profile of chromeless phase lithography (CPL) mask

Jimmy Lin, Michael Hsu, Tony Hsu, Stephen Hsu, Xuelong Shi, Douglas Van Den Broeke, J. Fung Chen, F. Tang, W. Hsieh, C. Huang

Proceedings Volume 5256, (2003) https://doi.org/10.1117/12.518021

KEYWORDS: Etching, Photomasks, Dry etching, Quartz, Semiconducting wafers, Lithography, Diffractive optical elements, Scanning electron microscopy, Metrology, Printing

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Proceedings Article | 28 August 2003 Paper

Investigation of phase variation impact on CPL PSM for low k1 imaging

Chun-hung Lin, Michael Hsu, Frank Hsieh, Shu Yi Lin, Stephen Hsu, Xuelong Shi, Douglas Van Den Broeke, J. Fung Chen, F. Tang, W. Hsieh, C. Huang

Proceedings Volume 5130, (2003) https://doi.org/10.1117/12.504176

KEYWORDS: Etching, Photomasks, Critical dimension metrology, Semiconducting wafers, Quartz, Printing, Image processing, Metrology, Process control, Phase shifting

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Proceedings Article | 28 August 2003 Paper

Low k1 lithography patterning option for the 90-nm and 65-nm nodes

Stephen Hsu, Douglas Van Den Broeke, Xuelong Shi, Michael Hsu, Kurt Wampler, J. Fung Chen, Annie Yu, Samuel Yang, Frank Hsieh

Proceedings Volume 5130, (2003) https://doi.org/10.1117/12.504394

KEYWORDS: Photomasks, Reticles, Manufacturing, Phase shifts, Lithography, Nanoimprint lithography, Etching, Quartz, Image transmission, Transmittance

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Proceedings Article | 26 June 2003 Paper

65-nm full-chip implementation using double dipole lithography

Stephen Hsu, J. Fung Chen, Noel Cororan, William Knose, Douglas Van Den Broeke, Thomas Laidig, Kurt Wampler, Xuelong Shi, Michael Hsu, Mark Eurlings, Jo Finders, Tsann-Bim Chiou, Robert Socha, Will Conley, Yen Hsieh, Steve Tuan, Frank Hsieh

Proceedings Volume 5040, (2003) https://doi.org/10.1117/12.485445

KEYWORDS: Reticles, Photomasks, Model-based design, Scattering, Optical proximity correction, Stray light, Resolution enhancement technologies, 3D modeling, Logic, Binary data

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Proceedings Article | 27 December 2002 Paper

Tuning MEEF for CD control at 65-nm node based on chromeless phase lithography (CPL)

Douglas Van Den Broeke, Thomas Laidig, Kurt Wampler, Stephen Hsu, Xuelong Shi, Michael Hsu, Paul Burchard, J. Fung Chen

Proceedings Volume 4889, (2002) https://doi.org/10.1117/12.467508

KEYWORDS: Reticles, Semiconducting wafers, Photomasks, Critical dimension metrology, Manufacturing, Lithography, Image processing, Scanners, Imaging systems, Wafer-level optics

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The application of Chromeless Phase Lithography, or 100% transmission attenuated PSM, has been used to demonstrate the potential for achieving quarter-wavelength optical lithography (0.2k₁). As the demand to image sub-100nm features reaches to the semiconductor fabrication lines, the need for a robust lithography process capable of meeting high volume requirements is becoming more and more critical. The requirements for high-volume, low-k₁ semiconductor manufacturing go beyond wafer imaging technology capable of the process latitude needed for lithography, but also includes data prep software that is capable of applying the details of the imaging technology to the design data, correcting for optical proximity effects, and outputting the necessary mask pattern data. It is also necessary to have a reticle manufacturing infrastructure capable of supporting large volume production with reliability and reasonable turn around time. CPL technology has, by its nature, many elements that make it a strong candidate to meet mass production requirements for 65nm semiconductor technology products. Most important, CPL achieves the resolution enhancement by using a single reticle and does not require a second exposure with a trim mask. The CPL reticle is a variation of the attenuated phase shifting mask, and data preparation for the reticle manufacturing is very similar to what is needed for high-transmission attenuated PSM. It will be shown that as a result of the 100% transmission, the MEEF for CPL masks is very small and in some cases approaches zero. This allows for much larger CD tolerances for the reticle but results in significant limitations on correcting optical proximity effects by using CD bias alone. Methods for correcting through-pitch CD variations with the use of novel CPL pattern designs, bias, and scattering bars will be presented and correlated to wafer imaging results. These results will demonstrate the ability to control through-pitch CD's while maintaining the beneficial MEEF characteristics of CPL. Experimental results using a CPL reticle designed and manufactured for 65nm lithography exposed on an advanced 193nm ASML /1100 wafer scanner will be presented and discussed.

Proceedings Article | 27 December 2002 Paper

Mesa or trench type for chromeless phase-shift lithography from photolithographic performance point of view

Xuelong Shi, J. Fung Chen, Stephen Hsu, Michael Hsu, Douglas Van Den Broeke, Robert Socha, Chun Hong Chang, Chang Min Dai

Proceedings Volume 4889, (2002) https://doi.org/10.1117/12.467393

KEYWORDS: Photomasks, Phase shifts, Optical lithography, Diffraction, Lithography, 3D image processing, Quartz, Etching, Electromagnetism, Optical proximity correction

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Proceedings Article | 27 December 2002 Paper

Phase defect repair for the chromeless phase lithography (CPL) mask

Steven Fan, Michael Hsu, Alex Tseng, J. Fung Chen, Douglas Van Den Broeke, Henrry Lei, Stephen Hsu, Xuelong Shi

Proceedings Volume 4889, (2002) https://doi.org/10.1117/12.467486

KEYWORDS: Photomasks, Quartz, Etching, Inspection, Lithography, Scanning electron microscopy, Printing, Semiconducting wafers, Mask making, Image processing

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Proceedings Article | 30 July 2002 Paper

Dipole decomposition mask design for full-chip implementation at 100-nm technology node and beyond

Stephen Hsu, Noel Corcoran, Mark Eurlings, William Knose, Thomas Laidig, Kurt Wampler, Sabita Roy, Xuelong Shi, Chungwei Michael Hsu, J. Fung Chen, Jo Finders, Robert Socha, Mircea Dusa

Proceedings Volume 4691, (2002) https://doi.org/10.1117/12.474596

KEYWORDS: Optical proximity correction, Photomasks, Reticles, Model-based design, Manufacturing, Semiconducting wafers, Scattering, Resolution enhancement technologies, Printing, Nanoimprint lithography

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Proceedings Article | 30 July 2002 Paper

Patterning half-wavelength DRAM cell using chromelessp phase lithography (CPL)

Chungwei Michael Hsu, Ronfu Chu, J. Fung Chen, Douglas Van Den Broeke, Xuelong Shi, Stephen Hsu, Troy Wang

Proceedings Volume 4691, (2002) https://doi.org/10.1117/12.474629

KEYWORDS: Photomasks, Optical proximity correction, Lithography, Optical lithography, Manufacturing, Printing, Computer aided design, Phase shifts, Resolution enhancement technologies, Lithographic illumination

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Proceedings Article | 16 July 2002 Paper

Understanding the forbidden pitch phenomenon and assist feature placement

Xuelong Shi, Stephen Hsu, J. Fung Chen, Chungwei Michael Hsu, Robert Socha, Mircea Dusa

Proceedings Volume 4689, (2002) https://doi.org/10.1117/12.473427

KEYWORDS: Scattering, Optical lithography, Destructive interference, Chromium, Reticles, Light scattering, Optical proximity correction, Image processing, Imaging systems, Printing

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Proceedings Article | 23 April 2002 Paper

Mask design optimization for 70-nm technology node using chromeless phase lithography (CPL) based on 100% transmission phase shifting mask

J. Fung Chen, Douglas Van Den Broeke, Michael Hsu, Thomas Laidig, Kurt Wampler, Xuelong Shi, Stephen Hsu, Ted Shafer

Proceedings Volume 4754, (2002) https://doi.org/10.1117/12.476927

KEYWORDS: Photomasks, Phase shifts, Lithography, Optical proximity correction, Optical lithography, Semiconducting wafers, Phase shifting, Printing, Image acquisition, Reticles

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Proceedings Article | 11 March 2002 Paper

Understanding the forbidden pitch and assist feature placement

Xuelong Shi, Stephen Hsu, J. Fung Chen, Chungwei Michael Hsu, Robert Socha, Mircea Dusa

Proceedings Volume 4562, (2002) https://doi.org/10.1117/12.458261

KEYWORDS: Scattering, Optical lithography, Destructive interference, Light scattering, Reticles, Optical proximity correction, Image processing, Imaging systems, Chromium, Printing

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Proceedings Article | 14 September 2001 Paper

Patterning 0.1-um device by using hybrid PSM

Chungwei Hsu, Ronfu Chu, Troy Wang, C. Liao

Proceedings Volume 4346, (2001) https://doi.org/10.1117/12.435744

KEYWORDS: Photomasks, Critical dimension metrology, Optical lithography, Printing, Semiconducting wafers, Nanoimprint lithography, Mask making, Phase shifts, Diffraction, Phase shifting

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Proceedings Article | 5 September 2001 Paper

RuMBa: a rule-model OPC for low MEEF 130-nm KrF lithography

Stephen Hsu, Xuelong Shi, Chungwei Michael Hsu, Noel Corcoran, J. Fung Chen, Sunil Desai, Micheal Sherrill, Y. Tseng, H. Chang, J. Kao, Alex Tseng, WeiJyh Liu, Anseime Chen, Arthur Lin, Jan Kujten, Eric Jacobs, Arjan Verhappen

Proceedings Volume 4409, (2001) https://doi.org/10.1117/12.438410

KEYWORDS: Photomasks, Optical proximity correction, Photoresist processing, Binary data, Semiconducting wafers, Reticles, Electroluminescence, Lithography, Calibration, Critical dimension metrology

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Proceedings Article | 14 June 1999 Paper

Improving the accuracy of overlay measurement through wafer sampling map rearrangement

Chungwei Hsu, Ronfu Chu, Jen Chen

Proceedings Volume 3677, (1999) https://doi.org/10.1117/12.350783

KEYWORDS: Overlay metrology, Optical alignment, Semiconducting wafers, Control systems, Image registration, Data modeling, Process control, Feedback control, Optical lithography, Signal processing

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Proceedings Article | 14 June 1999 Paper

Characterizing lens distortion to overlay accuracy by using fine measurement pattern

Ronfu Chu, Chungwei Hsu, Tsu-wen Hwang

Proceedings Volume 3677, (1999) https://doi.org/10.1117/12.350790

KEYWORDS: Overlay metrology, Monochromatic aberrations, Distortion, Error analysis, Tolerancing, Semiconducting wafers, Target detection, Measurement devices, Signal detection, Optical alignment

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Showing 5 of 36 publications

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