Design weak points that have narrow process window and limits wafer yield, or hotspots, continue to be a major issue in semiconductor photolithography. Resolution enhancement techniques (RET) such as advanced optical proximity correction (OPC) techniques and source mask optimization (SMO) are employed to mitigate these issues. During yield ramp for a given technology node, full-chip lithography simulation, pattern-matching and machine learning are adopted to detect and remedy the weak points from the original design , . This is typically an iterative process by which these points are identified in short-loop lithography testing. Design retarget and/or OPC modifications are made to enhance process window until the yield goal is met. This is a high cost and time consuming process that results in a slow yield ramp for existing production nodes and increased time to market (TTM) for new node introduction. Local hotspot correction through mask and wafer harmonization is a method to enhance wafer yield with low cost and short cycle time compared to the iterative method. In this paper, a fast and low cost approach to hotspot correction is introduced. Hotspots were detected on wafer after OPC and characterized by using advanced mask characterization and optimization (AMCO) techniques. Lithographic simulations and AIMS measurement were used to verify the hotspot correction method. Finally, the validity of this new approach was evaluated by process window analysis and circuit probe yield test at wafer.
A new technology transforms mask inspection images through focus into 3D lithography images in resist. This enables early detection and ranking of hotspots, and distinguishes mask-induced and process-induced hotspots. The results can be used in several ways including: 1) feed back to OPC teams to improve process window; 2) feed forward to the litho team for scanner adjustment; and, 3) feed forward to wafer inspection in the form of care areas to reduce time to result for wafer-based process window discovery.
As the process node becomes more advanced, the accuracy and precision in OPC pattern CD are required in mask
manufacturing. CD SEM is an essential tool to confirm the mask quality such as CD control, CD uniformity and CD
mean to target (MTT).
Unfortunately, in some cases of arbitrary enclosed patterns or aggressive OPC patterns, for instance, line with tiny
jogs and curvilinear SRAF, CD variation depending on region of interest (ROI) is a very serious problem in mask CD
control, even it decreases the wafer yield. For overcoming this situation, the 2-dimensional (2D) method by Holon is
adopted. In this paper, we summarize the comparisons of error budget between conventional (1D) and 2D data using CD
SEM and the CD performance between mask and wafer by complex OPC patterns including ILT features.
According to the ITRS roadmap, semiconductor industry drives the 193nm lithography to its limits, using techniques like Double Pattern Technology (DPT), Source Mask Optimization (SMO) and Inverse Lithography Technology (ILT). In terms of considering the photomask metrology, full in-die measurement capability is required for registration and overlay control with challenging specifications for repeatability and accuracy. <p> </p>Double patterning using 193nm immersion lithography has been adapted as the solution to enable 14nm technology nodes. The overlay control is one of the key figures for the successful realization of this technology. In addition to the various error contributions from the wafer scanner, the reticles play an important role in terms of considering lithographic process contributed errors. Accurate pattern placement of the features on reticles with a registration error below 4nm is mandatory to keep overall photomask contributions to overlay of sub 20nm logic within the allowed error budget.<p> </p> In this paper, we show in-die registration errors using 14nm DPT product masks, by measuring in-die overlay patterns comparing with regular registration patterns. The mask measurements are used to obtain an accurate model to predict mask contribution on wafer overlay of double patterning technology.
In the development of leading-edge devices, high-end mask is required and the spec request from mask users becomes more and more tight and complex. Mask users concern not only CD (critical dimension) uniformity, defect condition, registration/overlay, but also haze issue and better pattern profile. There are lots of items which are included in pattern profile, like line-end shortening, edge roughness, corner rounding and side-wall angle, etc. Mask shop's engineers always need to cut blanks and then get cross-section images at CD-SEM. But it wastes lots of time and money. In this paper we try to find the relationship between mask side-wall angle and simulated aerial image by using Carl Zeiss' Aerial Image Measurement System (AIMS<sup>TM</sup>-fab). For the further study, we compare three types of E-beam writers and two types of etchers to recognize its effect on side-wall angle.
For current mask defect repair, depending only on an inspection metrology tool (KLA-SLF77) to judge wafer printability is not enough. Many mask makers and users are turning to simulation-based photomask qualification to reduce unnecessary repairs and confirm defect repair. Using programmed defects of known size, phase, and location, we fabricated binary and Att PSM test masks to perform the repair. Utilizing Carl Zeiss’ Aerial Image Measurement System (AIMS-fab), we compared reticle simulation results to actual wafer image prints and then established a criteria SPEC as the core judgment rule. The investigation shows for binary L/S layout, the better repair profile received a wider ED-window for the wafer process. For Att PSM contact layout, the proper depth of quartz etching for smaller miss-contact was also demonstrated.
The etching loading effect is always a big issue for mask maker to get excellent critical dimension (CD) uniformity. For etching process, with different loading area density the etching rate is different and then micro-loading issue exists. In accordance with the shrinking of patterns on ultra-large scale integration (ULSI), higher CD accuracy on photomask is required. For the 130nm technology node, the SPEC of CD uniformity range is about 17 ~ 22nm. At common poly layer, the distribution of pattern density is from 50% ~ 90%. The CD variation with different pattern density is 15 ~ 20nm. Besides adjusting the etching recipe to minimize the loading effect, we provide another solution. With loading effect correction (LEC) function on HL-950M, it offers a software method to calculate the pattern density and produce a dosage map to compensate the CD variation which is resulted from etching loading.
The continuous shrinking of design rules results in tighter specifications for linearity in advanced mask processing. Specifically, the increasing need for multiple devices on a single reticle set, e.g., multiproject wafers (MPWs) and systems on a chip (SoC), drives development in this area. Advanced masks were prepared with positive and negative chemically amplified resist (CAR) written on the Hitachi HL-950M. Post-exposure bake was performed in a double-sided proximity baking system; development was done using a spray-puddle method. Etch experiments were performed in the Etec Systems Tetra photomask etch chamber. Linearity measurements were performed using the Hitachi S-7840 CD SEM and the Leica LWM 250 DUV. Both clear and dark isolated and dense features were measured.
The current work examines the impact of various etch process parameters (Cl<sub>2</sub>/O<sub>2</sub> ratio, gas flow, pressure, source power) on CD linearity between 400 nm and 1.25 μm. A full factorial-designed orthogonal experiment was performed to determine the main effects and any interactions that might impact the linearity performance. Pressure and total flow showed a strong influence on linearity.