Proc. SPIE. 10148, Design-Process-Technology Co-optimization for Manufacturability XI
KEYWORDS: Semiconductors, Lithium, Capacitors, Databases, Metals, Error analysis, Silicon, Manufacturing, Transistors, Resistors, Analog electronics, Digital electronics, System on a chip, New and emerging technologies
Analog circuits are sensitives to the changes in the layout environment conditions, manufacturing
processes, and variations. This paper presents analog verification flow with five types of analogfocused
layout constraint checks to assist engineers in identifying any potential device mismatch and
layout drawing mistakes. Compared to several solutions, our approach only requires layout design,
which is sufficient to recognize all the matched devices. Our approach simplifies the data preparation
and allows seamless integration into the layout environment with minimum disruption to the custom
layout flow. Our user-friendly analog verification flow provides the engineer with more confident with
their layouts quality.
As process technology scales down, the number of Chemical Mechanical Polishing (CMP) processes and steps used in chip manufacturing are increasing exponentially. Shrinking process margins increase the risk of excessive metal or oxide thickness or topography variations, causing potential yield problems such as dishing, erosion, resist lifting or printability issues.<p> </p>Present DFM CMP modeling and applications mainly focus on the hotspot detection and fixing methodology for the Back-End-Of-Line (BEOL) layers <sup></sup>. Today, the present methodology is no longer sufficient to eliminate all the CMP related manufacturing defects. There is a strong demand for STI, poly and contact silicon calibrated CMP models to predict and fix the related CMP hotspots.<p> </p>Shallow Trench Isolation (STI) and Poly CMP planarity is very critical in advanced technologies with Diffusion layer FIN structures and Replacement Metal Gate Process flow <sup></sup>. Gate uniformity after CMP will improve device performance, reduce CMP defects and increases the yield. Contact (Tungsten) CMP polishing is another important step that defines contact planarity, which will influence metal layer CMP planarization <sup></sup>.<p> </p> This paper will discuss design dependent CMP variations for STI, Poly and Contact CMP steps and showcase the importance of FEOL CMP modeling. We present the methodology for Silicon calibrated STI CMP, Poly and Contact CMP models and the applications of FEOL CMP models in CMP dishing and erosion hotspot analysis. We also present FEOL plus BEOL multi stack CMP simulations applications and provide design guidelines to fix CMP hotspots.
Proc. SPIE. 9781, Design-Process-Technology Co-optimization for Manufacturability X
KEYWORDS: Data modeling, Calibration, Etching, Metals, Copper, Silicon, Manufacturing, Design for manufacturing, Semiconducting wafers, Product engineering, Chemical mechanical planarization, Back end of line, Design for manufacturability
As we move to advanced technology nodes, the requirements on within chip and across wafer planarity are becoming more demanding . Also, the number of Chemical Mechanical Polishing (CMP) processes and steps used in microelectronic chip manufacturing is increasing rapidly, in an effort to meet the stringent planarity requirements . However, the complex pattern dependencies inherent in CMP processes, and the cumulative nature of the topography generated by these processes make it challenging to meet the aforementioned stringent uniformity requirements for the variety of designs produced. Consequently, we expect to see an increased CMP and related hotspots on advanced node designs. Accurately detecting CMP and related hotspots (such as pooling, DOF hotspots, topography variation hotspots etc.) and providing guidelines to fix or prevent them is therefore critical for CMP process development, yield ramp up and shorter design and manufacturing cycles.<p> </p> In this paper we present a hotspot detection and removal/prevention flow. The flow uses Cadence Design System’s manufacturing modeling methodology that predicts feature scale, within chip, and wafer level topography. The modeling methodology takes into account etch depth, deposition, and CMP variations across multiple levels in the design, and across multiple process steps within a given design level.
Proc. SPIE. 9427, Design-Process-Technology Co-optimization for Manufacturability IX
KEYWORDS: Lithography, Metals, Silicon, Manufacturing, Design for manufacturing, Chemical analysis, Nanoimprint lithography, Failure analysis, Chemical mechanical planarization, Design for manufacturability
DFM rule based scoring is associated with manufacturability rules checking and applying the scoring to predict the yield entitlement for an IC chip design. Achieving high DFM score is one of the key requirements to get high yield. The DFM scoring methodology is currently limited to DFM recommend rules and their associated failure rates. In contrast to failure mechanism, chemical-mechanical polishing (CMP) step topography variations places an important role to it. In this paper, we present an advanced DFM analysis flow to compute DFM score that incorporate topography variation along with recommend rule scoring using complex scoring model to increase silicon yield correlation.
Chemical Mechanical Polishing (CMP) is the essential process for planarization of wafer surface in semiconductor manufacturing. CMP process helps to produce smaller ICs with more electronic circuits improving chip speed and performance. CMP also helps to increase throughput and yield, which results in reduction of IC manufacturer’s total production costs. CMP simulation model will help to early predict CMP manufacturing hotspots and minimize the CMP and CMP induced Lithography and Etch defects <sup></sup>. In the advanced process nodes, conventional dummy fill insertion for uniform density is not able to address all the CMP short-range, long-range, multi-layer stacking and other effects like pad conditioning, slurry selectivity, etc. In this paper, we present the flow for 20nm CMP modeling using Mentor Graphics CMP modeling tools to build a multilayer Cu-CMP model and study hotspots. We present the inputs required for good CMP model calibration, challenges faced with metrology collections and techniques to optimize the wafer cost. We showcase the CMP model validation results and the model applications to predict multilayer topography accumulation affects for hotspot detection. We provide the flow for early detection of CMP hotspots with Calibre CMPAnalyzer to improve Design-for-Manufacturability (DFM) robustness.
CMP effects on manufacturability are becoming more prominent as we move towards advanced process nodes, 28nm and below. It is well known that dishing and erosion occur during CMP process, and they strongly depend on pattern density, line spacing and line width <sup></sup>. Excessive thickness or topography variations can lead to shrinkage of process windows, causing potential yield problems such as resist lifting or printability issues. When critical patterns fall into regions with extreme topography variations, they would be more sensitive to defects and could potentially become yield limiters or killers. Scanner tools compensate and correct topography variations by following the given profile <sup></sup>. However the scanner exposure window size is wider compared to local topography variations in design. This difference would generate new lithography focus sensitive weak points which may be missed. Experiments have been conducted as shown in Fig 1. Design under manufacturing has been subjected to scanner tool topography focus corrections. Despite of the corrections, Site B topography height has worsened while site A and C shown some improvements. As a result, additional improvements need to be done to meet manufacturability requirements.
To provide fabless designers the same advantage as Integrated Device Manufacturer (IDMs), a design-oriented litho
model has been calibrated and an automated lithography (litho) hotspot detection and fixing flow has been implemented
during final routing optimization.
This paper shows how a design-oriented litho model was built and used to automate a litho hotspot fixing design flow.
The model, calibrated and validated against post-OPC contour data at 99%, was embedded into a Litho Physical
Analyzer (LPA) tech file. It allowed the litho contour of drawn layouts to be simulated at full chip level to detect litho
hotspots and to provide fixing guidelines. Automated hotspots fixing was hence made possible by feeding the guidelines
to the fixing tools in an industry based integrated flow. Post-fixing incremental checks were also performed to converge
to a clean design.
Chemical Mechanical Polishing (CMP) has been used in the manufacturing process for copper (Cu) damascene process.
It is well known that dishing and erosion occur during CMP process, and they strongly depend on metal density and line
width. The inherent thickness and topography variations become an increasing concern for today's designs running
through advanced process nodes (sub 65nm). Excessive thickness and topography variations can have major impacts on
chip yield and performance; as such they need to be accounted for during the design stage.
In this paper, we will demonstrate an accurate physics based CMP model and its application for CMP-related hotspot
detection. Model based checking capability is most useful to identify highly environment sensitive layouts that are prone
to early process window limitation and hence failure. Model based checking as opposed to rule based checking can
identify more accurately the weak points in a design and enable designers to provide improved layout for the areas with
highest leverage for manufacturability improvement. Further, CMP modeling has the ability to provide information on
interlevel effects such as copper puddling from underlying topography that cannot be captured in Design-for-
Manufacturing (DfM) recommended rules.
The model has been calibrated against the silicon produced with the 45nm process from Common Platform (IBMChartered-
Samsung) technology. It is one of the earliest 45nm CMP models available today. We will show that the
CMP-related hotspots can often occur around the spaces between analog macros and digital blocks in the SoC designs.
With the help of the CMP model-based prediction, the design, the dummy fill or the placement of the blocks can be
modified to improve planarity and eliminate CMP-related hotspots. The CMP model can be used to pass design
recommendations to designers to improve chip yield and performance.
During the deep sub-micron semiconductor manufacturing process, the Chemical-Mechanical Polishing (CMP) is
applied on conductor layers to create a planar surface over the wafer. To ensure layer uniformity after CMP and to avoid
metal dishing and erosion effects, dummy metals are usually inserted to the layers either by designers or foundries.
However, adding dummy metal polygons can have undesirable impact to the capacitance and hence the timings of the
clock paths and signal paths in the design.
Chartered and Magma jointly developed and validated a methodology combining the router timing-aware track fill
followed by foundry metal fill to minimize the timing impact of the metal fill to the design as well as achieving high
quality copper uniformity.
In this paper, we will show the proposed metal fill methodology outperform the conventional approaches of metal fill or
track fill. The proposed metal fill was validated using Static Timing Analysis and an accurate silicon calibrated CMP
model is used for copper (Cu) thickness distributions comparisons. From the 65nm case study results, the timing impact
to the design in terms of total number of nets with slack degradation has been reduced from 4% to 0.24%. And the
copper uniformity in terms of standard deviation of the copper density has been improved from 0.192 to 0.142 on
average. The deployment of proposed metal fill is integrated seamlessly into the reference design flow.