A methodology to predict the impact of mask overlay and litho-induced process variations on Statistical
Timing for Double Patterning is presented. As we migrate to the 32nm node and Double Patterning
techniques, Mask Makers, Ebeam providers and Scanner providers are given very aggressive requirements
for maintaining overlay accuracy. This method takes into account Mask CD Uniformity and Mask Image
placement error budgets presented in the 2006 ITRS. It is assumed the ITRS requirements are met. This
methodology combines the infrastructure used in Single Exposure Litho-Aware Layout Implementation
tools with Double Patterning decomposition results to determine a meaningful layout-specific analysis for
pre-tape-out timing sign-off. Traditional timing analysis uses a set of look-up tables for simulating device
distortions. These tables have been proven to require excessive guardbanding in Single Exposure masks.
Adding the additional dimension of overlay distortion to these tables will have the effects of hiding
parametric failures, or requiring excessive guardbanding to ensure timing predictability. Results will be
shown that describe the timing effects with and without taking into account these distortions, as well as
design samples that contribute to these distortions.
Over the last half century, integrated circuit (IC) design has taken root from the invention of the solid-state transistor to multi-million transistor circuits. Accommodating this remarkable evolution of circuit design is the electronic design automation (EDA) industry. From the driving forces of fierce industry competition to the self-imposed adherence to Moore's Law, the EDA industry has provided design and productivity solutions spanning a multitude of disciplines. From the invention of hardware definition languages (HDL), to the extension of the marketable life of semiconductor exposure systems, the EDA industry has continued to meet ever-increasing semiconductor industry challenges.
This course provides an overview of integrated circuit design using software tools commonly available to the electronic design automation industry. Software tools, methods of design and their respective impact on integrated circuit design are discussed. The course covers a brief history of the EDA industry, with primary focus on traditional methods of implementation, verification and simulation of design content. The course discussions encompass a typical, holistic design flow prior to IC mask making and fabrication, and IC manufacturing problems and solutions addressed by the EDA industry.