Process window OPC (PWOPC) is widely used in advanced technology nodes as one of the most important resolution enhancement techniques (RET).1 PWOPC needs to consider not only edge placement error (EPE) from nominal condition simulations, but also constraints based on process variation simulations, such as pinch and bridge related requirements based on process variation band (PVBAND). Those constraints can be challenging to meet as feature size continues to shrink in advanced nodes.
In this paper a novel matrix retargeting based PWOPC was developed to find optimal OPC solutions by solving constraints-based matrix and applying minimal retargeting as needed.2 Experiment results showed enhanced process window and reasonable performance.
The 2x nm logic foundry node has many challenges since critical levels are pushed close to the limits of low k1 ArF water immersion lithography. For these levels, improvements in lithographic performance can translate to decreased rework and increased yield. Source Mask Optimization (SMO) is one such route to realize these image fidelity improvements. During SMO, critical layout constructs are intensively optimized in both the mask and source domain, resulting in a solution for maximum lithographic entitlement. From the hardware side, advances in source technology have enabled free-form illumination. The approach allows highly customized illumination, enabling the practical application of SMO sources. The customized illumination sources can be adjusted for maximum versatility. In this paper, we present a study on a critical layer of an advanced foundry logic node using the latest ILT based SMO software, paired with state-of-the-art scanner hardware and intelligent illuminator. Performance of the layer's existing POR source is compared with the ideal SMO result and the installed source as realized on the intelligent illuminator of an NSR-S630D scanner. Both simulation and on-silicon measurements are used to confirm that the performance of the studied layer meets established specifications.
It is evident that as industry moves towards 28 and 20 nm large scale production, more flexibility in source is eminent for better process margin. In this paper, we review different realms of illumination optimization techniques with combinations of currently available source shapes along with pixelated source optimization. However, it has been observed in the past that any optimized source heavily relies on the patterns that are used in optimization. Therefore, it is critical that early in the resolution enhancement technology (RET) selection flow, test patterns are carefully chosen. The patterns should maintain the balance of cycle time for source tuning and at the same time ensure fidelity in accuracy. This type of trade-off becomes easier with an automated pattern selection tool that can guarantee coverage and accuracy together. Different approaches of pattern selection are demonstrated in this paper and the knowledge is transferred to development activities for 28 nm layers. In this paper we investigate compatibility of sources that are tuned over a set of design database and its adaptability of optimized source over small variations in design. At the end we demonstrate a reliable solution that could be integrated early in RET development and easily adapted for the production environment.
Photolithography for the formerly "non-critical" implant blocking layers is becoming more challenging as edge
placement control budgets for junction definition shrink with each node. In addition to the traditional proximity
effects associated with the implant layer mask, the underlying active and gate layers can interact through a variety of
mechanisms to influence the edge placement of the developed implant layer. These mechanisms include bulk
reflectivity differences, resist thickness thin film interference effects, reflective notching from pattern sidewalls,
reflections from curved surfaces, focus differences, and more. While the use of organic developable bottom
antireflection coating (dBARC) can be effective in minimizing these influences, it does represent an added
complexity and cost, and processes are still relatively immature. Without such a dBARC, the CD variation due to
underlying layers can easily exceed 50 nm, or more than 25% of the target dimension. We propose here a
framework for modeling and correcting for these underlayer effects. The approach is based upon calibration of an
optical model representing only implant mask proximity effects and two additional optical models which represent
the effects of the underlayer topography. Such an approach can be effective in delivering much improved CD
control for complex layouts, and represents only a small impact to full-chip correction runtime.
The 22nm node will be patterned with very challenging Resolution Enhancement Techniques (RETs) such
as double exposure or double patterning. Even with those extreme RETs, the k1 factor is expected to be
less than 0.3. There is some concern in the industry that traditional edge-based simulate-then-move Optical
Proximity Correction (OPC) may not be up to the challenges expected at the 22nm node. Previous work
presented the advantages of a so-called inverse OPC approach when coupled with extreme RETs or
illumination schemes. The smooth mask contours resulting from inverse corrections were shown not to be
limited by topological identity, feedback locality, or fragment conformity. In short, inverse OPC can
produce practically unconstrained and often non-intuitive mask shapes. The authors will expand this
comparison between traditional and inverse OPC to include likely 22nm RETs such as double dipole
lithography and double patterning, comparing dimensional control through process window for each OPC
method. The impact of mask simplification of the inverse OPC shapes into shapes which can be reliably
manufactured will also be explored.
Due to complex interconnect wiring scheme and constraints from process rules, systematic defects such as pattern necking and bridging are a major concern for metal layers. These systematic defects or "weak spots" can be major yield detractors in IC manufacturing if not properly addressed. These defects can occur even in cases where model-based OPC has been implemented, as well as a variety of process rules for margin insurance. Determining how to improve the marginalities or "weak spots" becomes a key factor for enhancing product yields. This paper will address several root causes for pattern induced defects and present solutions to a variety of weak spots including "T-shape," "H-shape," "Thin-Line," and "Bowling Pin" defects during 65nm product development at TI. Through case studies, we demonstrate how to successfully provide DFM (Design for Manufacturing) by using Resolution Enhancement Techniques (RET) tools to avoid and minimize the weak spots. Furthermore, process techniques to improve printability for some of the weak spots as applied to 65nm reticle sets will be discussed. An integrated scheme aiming at optimization of design rules and process rules is proposed.
Swing curve generation is an important and common exercise in the design, characterization, and optimization of photolithography processes. The development of a robust anti-reflective strategy for a given process often necessitates multiple experimental iterations of the swing curve generation. The traditional methodology for generating a photoresist thickness swing curve plot is time and silicon intensive; usually involving processing and metrology on a dozen or more wafers. In addition, the resulting curve often can convolve systematic and random wafer-wafer effects due to other track/resist/scanner related variables. In some cases, such as very low reflectivity underlying substrate the signal to noise ratio is poor enough to effectively mask the sinusoidal swing behavior from visibility. In this paper, we present a new methodology to generate a swing curve by using a single wafer. The critical point of this method is to generate a temperature gradient on the wafer during the initial step of photoresist dispense and coating. Since the resist viscosity is inversely proportional to the temperature, a significant resist thickness variation can be produced across the wafer, which can easily encompass one swing period of thickness or more. The resulting resist thickness signature across the wafer is seen to be very repeatable, such that a companion wafer can be measured at multiple positions corresponding to CD metrology lcoations on the patterned wafer. The possibility of deconvolving systematic across wafer CD variability due to other process variables is discussed by characterizing a control wafer with conventional uniform resist thickness. Our experiments for I-line and DUV resists indicated that this method not only provides reliable swing curves but also saves photoresist, silicon, and time both for engineering and machine. Moreover, this methodology represents an improved signal to noise ratio such that makes it particularly useful for ARC thickness/composition optimization. Several examples utilizing this method will be presented.