Single photon avalanche diodes (SPADs) manufactured through the standard CMOS process have a major advantage in reducing the cost and expendability in comparison with the SPAD made with the custom process.
SPAD is a single photon sensitive diode using the avalanche phenomenon and operated in Geiger-mode which applies a voltage higher than the breakdown voltage of the device. Therefore, SPAD is exposed to a higher voltage than other devices and has a high electric field in the multiplication region.
In SPAD operating with such a high electric field, the guard ring prevents edge breakdown and serves to focus the electric field on the intended multiplication region. Therefore, the optimized guard ring structure is required for the high efficiency SPAD designs. The deep virtual guard ring is designed to cope with deeper multiplication regions formed by deep n-well and p-well, thus providing higher photon detection probability (PDP) and enhanced response at a longer wavelength.
In this paper, the four possible Silicon-based SPAD candidates of different deep virtual guard rings formed by the combination of shallow trench isolation (STI) and p-substrate layer fabricated through standard CMOS process are investigated and their electric characteristics of the SPAD, such as the current-voltage (I-V) characteristic, and optical characteristics, such as dark count rate (DCR), and PDP, are measured.
In addition, TCAD simulations are used to verify the characteristic variation by analyzing the electric field profiles. Based on the results, the optimized structure of the SPAD with the deep virtual guard ring can be proposed.