Sub-resolution assist feature (SRAF) insertion techniques have been effectively used for a long time now to increase process latitude in the lithography patterning process. Rule-based SRAF and model-based SRAF are complementary solutions, and each has its own benefits, depending on the objectives of applications and the criticality of the impact on manufacturing yield, efficiency, and productivity. Rule-based SRAF provides superior geometric output consistency and faster runtime performance, but the associated recipe development time can be of concern. Model-based SRAF provides better coverage for more complicated pattern structures in terms of shapes and sizes, with considerably less time required for recipe development, although consistency and performance may be impacted. In this paper, we introduce a new model-assisted template extraction (MATE) SRAF solution, which employs decision tree learning in a model-based solution to provide the benefits of both rule-based and model-based SRAF insertion approaches. The MATE solution is designed to automate the creation of rules/templates for SRAF insertion, and is based on the SRAF placement predicted by model-based solutions. The MATE SRAF recipe provides optimum lithographic quality in relation to various manufacturing aspects in a very short time, compared to traditional methods of rule optimization. Experiments were done using memory device pattern layouts to compare the MATE solution to existing model-based SRAF and pixelated SRAF approaches, based on lithographic process window quality, runtime performance, and geometric output consistency.
As technology node has been shrinking for bit growth, various technologies have been developed for high productivity. Nevertheless, lithography technology is close to its limit. In order to overcome these limits, EUV(Extreme Ultraviolet Lithography) and DSA(Directed Self-Assembly) are being developed, but there still exists problems for mass production. Currently, all lithography technology developments focus on solving the problems related to fine patterning and widening process window.
One of the technologies is NTD(Negative Tone Development) which uses inverse development compared to PTD(Positive Tone Development). The exposed area is eliminated by positive developer in PTD, whereas the exposed area is remained in NTD. It is well known that NTD has better characteristics compared to PTD in terms of DOF(Depth of Focus) margin, MEEF(Mask Error Enhancement Factor), and LER(Line End Roughness) for both small contact holes and isolated spaces . Contact hole patterning is especially more difficult than space patterning because of the lower image contrast and smaller process window . Thus, we have focused on the trend of both NTD and PTD contact hole patterns in various environments. We have analyzed optical performance of both NTD and PTD according to size and pitch by SMO(Source Mask Optimization) software. Moreover, the simulation result of NTD process was compared with the NTD wafer level performance and the process window variation of NTD was characterized through both results. This result will be a good guideline to avoid DoF loss when using NTD process for contact layers with various contact types.
In this paper, we studied the impact of different sources on various combinations of pattern sizes and pitches while estimating DOF trends aside from source and pattern types.
The study of OPC (Optical Proximity Correction) model that well predict the wafer result has been
researched. As the pattern design shrink down, the need for the CD (Critical Dimension) controllability
increased more than before. To achieve these requirements, OPC models must be accurate for full chip
process and model inaccuracies are one of several factors which contribute to errors in the final wafer image.
For that reason, robust OPC using real lithographic terms was proposed. Real lithographic system is quite
different from ideal system that is used for OPC modeling. Until now, this difference was acceptable since
pattern size used for OPC model was large, but as device size shrinks, this gap between ideal and real system
causes degradation of OPC accuracy. So, various optical parameters such as apodization, laser band width,
degree of polarization, illumination are used today in order to compensate for this issue. Especially, major
issue in modeling error is related to how the illumination source is used. For this study we assess accuracy of optical model for robust OPC using ideal and actual illumination
sources, and test conditions are as follows: 1) We examined the difference of pupil types to output model respectively; 2) A parameterized test pattern layout was used by 1D test pattern types that have various lines and spaces; 3) All models were calculated in automation method so as to exclude the dependency of user skills; 4) OPC accuracies were examined by gate layer patterns on full chip level. The study is performed for 5X~4Xnm nodes lithographic processes. The main focus of the study was on usability of model that is made by measured source data in semiconductor manufacturing. Results clearly showed that the actual source for the optical model has merits and demerits.
Recently, the dramatic acceleration in dimensional shrink of DRAM memory devices has been observed. For sub 60 nm memory device, we suggest the following method of optical proximity correction (OPC) to enhance the critical dimension uniformity (CDU). In order to enhance CD variation of each transistor, hundreds of thousand transistor CD data were used through design based metrology (DBM) system. In a traditional OPC modeling method, it is difficult to realize enhancement of CD variation on chip because of the limitation of OPC feedback data.
Even though optical properties are surely understood from recent computational lithography models, there are so many abnormalities like mask effect, thermal effect from the wafer process, and etch bias variation of the etching process. Especially, etch bias is too complicate to predict since it is related to variations such as space among adjacent patterns, the density of neighboring patterns and so on.
In this paper, process proximity correction (PPC) adopting the pattern to pattern matching method is used with huge amount of CD data from real wafer. This is the method which corrects CD bias with respect to each pattern by matching the same coordinates. New PPC method for enhancement of full chip CD variation is proposed which automatically corrects off-targeted feature by using full chip CD measurement data of DBM system. Thus, gate CDU of sub 60 nm node is reduced by using new PPC method. Analysis showed that our novel PPC method enhanced CD variation of full chip up to 20 percent.
In the past when design rule is not tight, CD-based OPC modeling was acceptable. But shrinkage of design rule
eventually led to small process window, which in part increased MEEF(Mask Error Enhancement Factor). Hence, data
for OPC modeling have also become more complex and diverse in order to characterize the critical OPC models. The
number of measurement points for OPC model evaluation has increased to several hundred points per layer, and
metrology requests for realizing pattern shapes on the wafer are no longer simple one-dimensional measurements.
Traditional CD-based OPC modeling is based on 1 dimensional parameter fitting and has limited information. Due to
this reason, the accuracy of the model has intrinsic limitations. Recently, development of modeling methodology
resulted in SEM image calibration. SEM image calibration use SEM image to calibrate large volume 2 dimensional
information. SEM image calibration is based on real SEM image which has several thousands of CD information. It
needs only SEM images instead of several hundred CD data, so data feedback is more easy. But this approach makes it
difficult to achieve confidential level for predictability because SEM image is restricted to local region. And modeling
accuracy is highly dependent on SEM image quality and local position.
In this paper, we propose SEM image calibration method that feeds back SEM image calibrated model to
model-based verification. By using this method, modeling accuracy is increased and better post OPC verification can be
made. We will discuss the application result on sub-60nm device and the feasibility of this approach.