Hardmask processes are a key technique to enable low-k semiconductors, but they can have an impact on patterning control, influencing defectivity, alignment, and overlay. Specifically, amorphous carbon layer (ACL) hardmask schemes can negatively affect overlay by creating distorted alignment signals. A new scheme needs to be developed that can be inserted where amorphous carbon is used but provide better alignment performance. Typical spin-on carbon (SOC) materials used in other hardmask schemes have issues with DCD-FCD skew. In this paper we will evaluate new spin-on carbon material with a higher carbon content that could be a candidate to replace amorphous carbon.
The k1 factor of the 65nm node device approaches to around 0.3 or even below because the device shrinking is much faster than the development speed of the high NA ArF scanner. Since the conventional model-based OPC (MBOPC) is only focused on patterning of the layout on the wafer as exactly same as the original design, it can hardly guarantee enough process margin in the low-k1 lithography regime. In this paper, illumination shape and retargeting rule of the multi-step OPC are optimized to improve the process margin of the 65nm node memory device. Sigma width and open angle of the dipole illumination is optimized to resolve the minimum pitch and to maintain the critical dimension (CD) uniformity. Even though the illumination is optimized and litho-friendly layout (LFL)  is applied, there is the process weak point caused by the device architecture. Applying the full-chip level verification, it is found that most of process weak points exist in isolated and semi-dense patterns of the core and peripheral region. The full-chip level verification uses the vector thin film model for the accurate resist image simulation of the high NA scanner. As the mask error enhancement factor (MEEF) is getting larger in the 65nm node device, the mask mean to target (MTT) rises as the dominant factor of the process margin. The NILS according to mask MTT variation is adopted as criterion for the process weak point extraction. Since the NILS of process weak point can be improved by the increasing pattern with, retargeting rules such as selective bias and pattern shift are applied. Under the dipole illumination, the NILS distributions of parallel and perpendicular patterns are different and the different retargeting rules are applied to them. Applying proposed illumination and multi-step OPC optimization to the 65nm node memory device, we have validated that our methodology can insure enough process margin for the volume production.
In spite of the advantages of low cost and resistance, dual damascene process has some problems. When contact holes are patterned within the trench patterns, the contact holes are frequently found to be unopen and are bent toward trench side wall (TSW). These cause CD variation and small depth of focus. We can explain this phenomenon in view of limited resolution of photoresist (PR) and the light reflected from the TSW. The deeper the trench depth is, the thicker the thickness of the photoresist for contact hole patterns is, which leads to decreased resolution. And the light reflected off the TSW makes the contact hole's profile bent toward TSW. This reflected light influences on both sides. One is helpful in defining the contact holes near the TSW, and the other causes CD variations according to distance between the contact holes and TSW. If the contact holes and trench patterns are exactly the same sizes, it is possible to decrease the CD variation and to prevent PR contact holes from unopening within the trench patterns. Also it is of help to improve resolution at the bottom of the PR.
Bake process of photo resist above glass transition temperature (Tg) increases its fluidity and shrinks contact holes patterned on the wafer. This process enables us to define sub-0.2 micrometers contact hole pattern with KrF, which is one of major issues of sub-0.15 micrometers device technology. However, the amount of PR flow depends on the contact hole size, pattern density and environment, which makes it difficult to control the fine critical dimension (CD) variation. In this paper, new approach to overcome the difficulties is studied with acetal type PR and attenuated phase shift mask (att. PSM). It is found that the change of chemical bonding in PR by light exposure decreases the resist flow sensitivity, which makes us solve the problems. The att. PSM enables us to control the aerial image intensity between contact holes, and the CD variation induced by bake process was drastically decreased when it is compared to Cr mask. The layout optimization by simulation for aerial image control in bulk region, and the resist flow process combined with att. PSM allows us to control the CD variation less than 20 nm for the sub-0.15 micrometers devices fabrication.
We have investited the performance of the halftone phase-shifting mask (HT PSM) with various illuminations for contact patterns of different pitches in DUV photo lithography . It was found that illumination could be optimized as a function of the pitch. Highly coherent illumination was the best for isolated contact patterns but it was the worst for extremely dense contact patterns due to optical proximity effect and interference which occurred between the primary peaks and the secondary peaks of neighboring contact holes. For extremely dense contact patterns, off-axis illumination (OAI) was found to be the most appropriate compared to conventional illuminations because extremely dense contact patterns show the optical proximity effects which was observed similarly for equal line and space patterns. We found that HT PSM combined with OAI can be used for fabricating the extremely dense contact patterns of high density devices such as 256M and 1 G bit DRAM.