Process dependent focus leveling errors occur in photolithography when there is unpredicted reflectivity
originating from multilayer structures on the fully integrated process wafer. The typical wavelength used in optical focus
sensors is in the near infrared (NIR) range which is highly transparent to most dielectric materials. Consequently, the
reflected light from underlying structures perturbs the accuracy of the leveling signal reflected from resist surface. To
alleviate this issue, air-gauge focus sensors have been used to measure the wafer surface topography for an in-situ
calibration to correct the focus leveling error. Using an air-gauge sensor is a slow process and a throughput detractor.
Therefore, an NIR-absorbing underlayer has been developed for easy insertion into existing resist coating processes. It
has been demonstrated that the air-gauge sensor can be turned off without showing any degradation in leveling data or
litho performance on back end of line (BEOL) integrated wafers.
As chip size and pattern size continue to shrink, the thickness of photo resist is getting thinner and thinner. One of the
major reasons is to prevent the small resist features from collapse. It's very challenging to get enough etch resistance
from such thin resist thickness. An approach of Si-tri-layer stack which consists of resist, Si ARC (Si contenting
anti-reflection coating), organic underlayer from top to bottom has been adopted by many IC makers in the
manufacturing of 45 nm node. Even higher resist etching selectivity is needed for 32 nm node. Si ARC, of Si content
as high as 43%, provides good etch selectivity. At the same time, tri-layer also provides good control over reflectivity
in high NA immersion lithography. However, there are several well know issues concern Si-rich ARC. Resist
compatibility and shelf life are on top of the list. An aim of our development work was to overcome those issues in
order to produce manufacturing-worthy Si-rich ARC. Several synthesis methods were investigated to form Si-rich ARC
film with different properties. Collapse of resist patterns is used as an indicator of lithographic compatibility.
Lithographic performance was checked by accelerated shelf life tests at high temperature in order to predict the shelf life
at room temperature. It was found that adhesion between resist and Si-rich ARC is improved when contact angle of
Si-rich ARC is increased to more than 60 degree. Certain synthesis methods improve shelf life. After optimization of
film properties and synthesis methods of Si-rich ARC, SHB-A940 series have best litho compatibility and shelf life is six
months at storage temperature below 10°C.
Immersion lithography for the 32nm node and beyond requires advanced methods to control 193 nm radiation
reflected at the resist/BARC interface, due to the high incident angles that are verified under high numerical aperture
(NA) imaging conditions. Swing curve effects are exacerbated in the high NA regime, especially when highly reflective
substrates are used, and lead to critical dimension (CD) control problems. BARC reflectivity control is also particularly
critical when underlying surface topography is present in buried layers due to potential reflective notching problems. In
this work, a graded spin-on organic BARC was developed to enable appropriate reflectivity control under those
conditions. The graded BARC consists of two optically distinct polymers that are completely miscible in the casting
solution. Upon film coating and post-apply baking, the two polymers vertically phase-separate to form an optically
graded layer. Different characterization techniques have been applied to the study of the distribution of graded BARC
components to reveal the internal and surface composition of the optically graded film, which includes Variable Angle
Spectroscopic Ellipsometry (VASE) and Secondary Ion Mass Spectroscopy (SIMS). Also, optical constant optimization,
substrate compatibility, patterning defectivity and etch feasibility for graded BARC layers are described. Superior 193
nm lithographic performance and reflectivity control of graded BARC beyond 1.20 NA compared to conventional
BARCs is also demonstrated.
The semiconductor industry has used optical lithography to create impressively small features. However, the resolution of optical lithography is approaching limits based on light wavelength and numerical aperture. Immersion lithography is a means to extend the resolution by inserting a liquid with a high index of refraction between the lens and wafer. This enables the use of higher numerical aperture optics. Several engineering obstacles must be overcome before immersion lithography can be used on an industry-wide scale. One such challenge is the deposition of the immersion liquid onto the wafer during the scanning process; any residual liquid left on the wafer is a potential defect mechanism. The residual liquid deposition is controlled by the details of the fluid management system, and is strongly dependent on the three-phase contact line. Therefore, this work concentrates on understanding the behavior of this contact line, specifically by measuring the dynamic contact angle and the critical velocity for liquid deposition. A contact angle measurement technique is developed and verified; the technique is subsequently applied to measure the dynamic advancing and receding contact angle for a series of resist-covered surfaces under conditions that are relevant to immersion lithography.
The critical dimension (CD) of contact holes for the 65-nm application specific integrated circuit (ASIC) is 100 nm according to the 2002 update of the International Technology Roadmap for Semiconductors. The common through-pitch depth of focus (DOF) of such contact holes is very small using the current ArF exposure tool. High-numerical-aperture (NA) ArF exposure tools are not expected to improve the common DOF that scales by the square of the numerical half aperture. High-transmission attenuated phase-shifting masks increase the DOF of isolated contact holes. Off-axis illumination such as annular or quadrupole illumination improves the DOF of dense contact holes. Nonetheless, both the isolated and the dense contact holes need to be printed within spec on logic circuit.
To delineate 100-nm contact holes at several different pitches, we proposed the pack-and-unpack (PAU) process which employs double exposures. First, dummy holes are added to the surroundings of isolated contact holes facilitating the patterning of the resultant dense pattern with a resolution enhancement technique that favors dense contact holes. For example, dense holes are packed to 180-nm pitch and imaged with high-NA lens setting and quadrupole illumination. Then, the second image is used to open the desired holes or block the dummy contact holes. The purpose of this study was to develop new methods and new materials for the patterning of the second image. Three approaches were investigated. The first approach was forming an isolation layer to protect the first image; second, applying UV curing to harden the first image; third, using alcohol-based resists to pattern the second image. Among those three approaches of printing the second image, using resist in alcohols is the most convenient method. Even though the CD control of the second image is not so critical, resolution and process window of resists may need further improvement for 45-nm node and below. Using the second approach allows conventional ArF resists, which does not raise as many concerns as the alcohol-based resists. With the first approach, a lot more work is needed to prevent intermixing and reactions between the isolation layer and the resist for the second image. The results of this work point to the directions for material developments of the PAU process. Both the alcohol-based resists and UV curing are good approaches for PAU. Further characterizations such as DOF, exposure latitude (EL), and mask error factor (MEF) on them will be carried out in the near future.
The IC industry is moving toward 90nm node and below. The CD size of implant layers has shrunk to 220nm. To achieve better CD uniformity, dyed KrF resist and top anti-reflective coating (TARC) are commonly used in advanced photo process of implant layers. It’s well known that bottom anti-reflective coating (BARC) has better reflection control over TARC. However, dry etching process is required if typical organic BARC is applied to photo process of implant layers. It is undesirable for two reasons. The first reason is the substrate damage caused by plasma etching could affect the device performance. The second reason is higher cost due to additional processing steps. In order to overcome those two shortcomings, developable BARC (DBARC) is introduced. It is a new type of BARC, which is soluble to developer, TMAH solution, in the resist development step. There are some reports on the developer-soluble KrF BARC. Most of them are polyamic acid and their solubility to alkline could be adjusted by changing bake condition. However, its development is isotropic, which make it difficult to get a vertical profile. Therefore, we have developed a photosensitive developer-soluble BARC (DBARC) which is anisotropic after exposure and thus results in a nice vertical profile. The photosensitive DBARC utilizes the same concept as chemically amplified resist. It has acid-cleavable groups in the resin and PAGs in the formulation. The photosensitive DBARC turns soluble to TMAH developer after exposure and resist PEB. The solubility difference caused by exposure makes developing process anisotropic and thus improves profile control. In this article, we will report the evaluation results of various combinations of KrF resists and DBARC for implant layers. Since both the resist and DBARC are photosensitive, matching of the photo speeds of them is essential. The amount and type of PAG in both the resist and the DBARC play a very import role. Finally, the optimized combination showed acceptable lithography process window and good CD uniformity over topography.
Controlling critical dimension (CD) uniformity and overlay accuracy are crucial to achieving quality lithography. The continuous reduction in minimum feature and unit cell sizes on semiconductor wafers has posed significant strain to lithography engineers. According to the 2001 ITRS roadmap, the half pitch of DRAM will be 100 nm and the overlay requirement will be 35 nm for the Poly layer in 2003. Up to date, the 193 nm lithography is mainly applied to those critical layers, such as Poly, Contact, Metal and Via in chip process flow. For the non-criticals, such as well and source-drain implant layers, we still use 248 nm or even 365 nm lithography. Such a situation poses potential challenges when we try to improve the overlay accuracy demanded by area reduction on unit cells since a mix-and-match between 193 nm and 248 nm has to be carried out. In the 90 nm logic process, the overlay requirement of implant layer to critical layers are tightened to 60 nm, which has been close to the current limit of tool matching capability between 193 nm and 248 nm. Stimulated by such an issue we start to implement 193 nm lithography into implant layers. In this paper, a full lithographic process characterization for 90 nm logic implant layers using 193 nm lithography is reported. The photo resist swing cure was first generated to determine the resist thickness. A top antireflective coating (ARC) was also applied to reduce the photo resist swing effect. After the target thickness of photo resist is being defined, three different thickness of resist was coated including targeted, thinner and thicker than targeted. Resist coated wafers were through bombardment of implantation species, then were sent to SIMS analysis. Based on the SIMS results, the target thickness is verified to be safe for the high voltage implantation required by process flow. The DOF data were collected for six kinds of patterns. The proximity effect data of 193 nm is only half of that resulted in 248 nm lithography. So, the optical proximity correction (OPC) may not be needed if 193 nm lithography is used. Besides, the CD variation is also improved when compared to the 248 nm lithography, especially when resist patterns are printed on topographic wafers. As the chip continues its shrinkage, the 193 nm lithography will be a must for implant layers at some point.