In the pursuit of alternatives to traditional optical lithography, block copolymer directed self-assembly (DSA) has emerged as a low-cost, high-throughput option. However, issues of defectivity have hampered DSA's viability for large-scale patterning. Recent studies have shown copolymer fill level to be a crucial factor in defectivity, as template overfill can result in malformed DSA structures and poor LCDU after etching. For this reason, it is previously demonstrated the use of sub-DSA resolution assist features (SDRAFs) as a method of evening out template density. In this work, we propose an algorithm to place SDRAFs in random logic contact/via layouts. By adopting this SDRAF placement scheme, we can significantly improve the density unevenness and the resources used are also optimized. This is the first work to investigate the placement of SDRAFs in order to mitigate the DSA density variation problem, and it can be adopted for the mass deployment of DSA.
As one of the most promising next generation lithography technologies, multiple patterning lithography (MPL) plays an important role in the attempts to keep in pace with 10 nm technology node and beyond. With feature size keeps shrinking, it has become impossible to print dense layouts within one single exposure. As a result, MPL such as double patterning lithography (DPL) and triple patterning lithography (TPL) has been widely adopted. There is a large volume of literature on DPL/TPL layout decomposition, and the current approach is to formulate the problem as a classical graph-coloring problem: Layout features (polygons) are represented by vertices in a graph G and there is an edge between two vertices if and only if the distance between the two corresponding features are less than a minimum distance threshold value <i>d<sub>min</sub></i>. The problem is to color the vertices of G using k colors (k = 2 for DPL, k = 3 for TPL) such that no two vertices connected by an edge are given the same color. This is a rule-based approach, which impose a geometric distance as a minimum constraint to simply decompose polygons within the distance into different masks. It is not desired in practice because this criteria cannot completely capture the behavior of the optics. For example, it lacks of sufficient information such as the optical source characteristics and the effects between the polygons outside the minimum distance. To remedy the deficiency, a model-based layout decomposition approach to make the decomposition criteria base on simulation results was first introduced at SPIE 2013.<sup>1</sup> However, the algorithm<sup>1</sup> is based on simplified assumption on the optical simulation model and therefore its usage on real layouts is limited. Recently AMSL<sup>2</sup> also proposed a model-based approach to layout decomposition by iteratively simulating the layout, which requires excessive computational resource and may lead to sub-optimal solutions. The approach<sup>2</sup> also potentially generates too many stiches. In this paper, we propose a model-based MPL layout decomposition method using a pre-simulated library of frequent layout patterns. Instead of using the graph G in the standard graph-coloring formulation, we build an expanded graph H where each vertex represents a group of adjacent features together with a coloring solution. By utilizing the library and running sophisticated graph algorithms on H, our approach can obtain optimal decomposition results efficiently. Our model-based solution can achieve a practical mask design which significantly improves the lithography quality on the wafer compared to the rule based decomposition.