To satisfy the tight budget of critical dimension, an immersion exposure process is widely applied to critical layers
of the recent advanced devices to accomplish the high performance of resolution. In our 40nm node logic devices,
the overlay accuracy of the critical layers (immersion to immersion) would be required to be less than 15nm
(Mean+3sigma) and the one of the sub-critical layers (dry to immersion) would be required to be less than 20nm
(Mean+3sigma). Furthermore, the overlay accuracy of the critical layers might be less than 10nm (Mean+3sigma) in
the 32nm node logic devices. The method of improving the overlay performance should be investigated for mass
production in the future.
In this report, attaching weight to productivity, we selected the technique of high order process correction with
machine configuration and applied it for 40 nm node production. We evaluated the overlay performance of the
critical layers using 40nm process stack wafer and found that high order grid compensation was effective for
reducing the process impact on the overlay accuracy. Furthermore, about the sub-critical layers, high order grid
compensation was also effective for controlling the tool matching error.