Two different mask inspection techniques are developed and compared for 14 nm node and beyond photomasks, High
resolution and Litho-based inspection. High resolution inspection is the general inspection method in which a 19x nm
wavelength laser is used with the High NA inspection optics. Litho-based inspection is a new inspection technology.
This inspection uses the wafer lithography information, and as such, this method has automatic defect classification
capability which is based on wafer printability. Both High resolution and Litho-based inspection methods are compared
using 14 nm and 7 nm node programmed defect and production design masks. The defect sensitivity and mask
inspectability is compared, in addition to comparing the defect classification and throughput. Additionally, the Cost /
Infrastructure comparison is analyzed and the impact of each inspection method is discussed.
MEEF, or Mask Error Enhancement Factor, is simply defined as the ratio of the change in printed wafer
feature width to the change in mask feature width scaled to wafer level. It is important in chip
manufacturing that leads to the amplification of mask errors, creating challenges with both achieving
dimensional control tolerances and ensuring defect free masks, as measured by on-wafer image quality. As
lithographic imaging continues to be stressed, using lower and lower k1 factor resolution enhancement
techniques, the high MEEF areas present on advanced optical masks creates an environment where the
need for increased mask defect sensitivity in high-MEEF areas becomes more and more critical.
There are multiple approaches to mask inspection that may or may not provide enough sensitivity to detect
all wafer-printable defects; the challenge in the application of these techniques is simultaneously
maintaining an acceptable level of mask inspectability. The higher the MEEF, the harder the challenge will
be to achieve and appropriate level of sensitivity while maintaining inspectability…and to do so on the
geometries that matter.
The predominant photomask fabrication inspection approach in use today compares the features on the
reticle directly with the design database using high-NA optics. This approach has the ability to detect small
defects, however, when inspecting aggressive OPC, it can lead to the over-detection of inconsequential, or
nuisance defects. To minimize these nuisance detections, changing the sensitivity of the inspection can
improve the inspectability of a mask inspected in high-NA mode, however, it leads to the inability to detect
subtle, yet wafer-printable defects in High-MEEF geometry, due to the fact that this ‘desense’ must be
applied globally. There are also ‘lithography-emulating’ approaches to inspection that use various means to
provide high defect sensitivity and the ability to tolerate inconsequential, non-printing defects by using
scanner-like conditions to determine which defects are wafer printable. This inspection technique is
commonly referred to as being ‘lithography plane’ or ‘litho plane,’ since it’s assessing the mask quality
based on how the mask appears to the imaging optics during use, as proposed to traditional ‘reticle plane’
inspection which is comparing the mask only with its target design.
Regardless of how the defects are detected, the real question is when should they be detected? For larger
technology nodes, defects are considered ‘statistical risks’…i.e., first they have to occur, and then they
have to fall in high-MEEF areas in order to be of concern, and be below the detection limits of traditional
reticle-plane inspection. In short, the ‘perfect storm’ has to happen in order to miss printable defects using
well-optimized traditional inspection approaches. The introduction of lithographic inspection techniques
has revealed this statistical game is a much higher risk than originally estimated, in that very subtle waferprintable
CD errors typically fall into the desense band for traditional reticle plane inspection. Because printability is largely influenced by MEEF, designs with high-MEEF values are at greater risk of traditional
inspection missing printable CD errors. The question is… how high is high… and at what MEEF is optical
inspection at the reticle plane sufficient? This paper will provide evaluation results for both reticle-plane
and litho-plane inspections as they pertain to varying degrees of MEEF. A newly designed high-MEEF
programmed defect test mask, named VAMPIRE, will be introduced. This test mask is based on 7 nm node
technology and contains intentionally varying degrees of MEEF as well as a variety of programmed defects
in high-MEEF environments…all of which have been verified for defect lithographic significance on a
Zeiss AIMS system.
Early in a semiconductor node’s process development cycle, the technology definition is locked down using somewhat risky assumptions on what the process can deliver once it matures. In this early phase of the development cycle, detailed design rules start to be codified while the wafer patterning process is still being fine-tuned. As the process moves along the development cycle, and wafer processes are dialed-in, key yield improvement efforts focus on variability reduction. Design retargeting definitions are tweaked and finalized, and the use of finely tuned etch models to compensate for process bias are applied to accurately capture the more mature wafer process. The resulting mature patterning process is quite different from the one developed during the early stages of the technology definition. In this paper we describe an approach and flow to drive continuous improvement in the mask solution (OPC and MBSRAF) later in the process development and production readiness cycle stage. First, we establish the process window entitlement within the design-space by utilizing advanced mask optimization (MO) combined with the baseline process (i.e., model, etch compensation, and design retargeting). Second, gaps to the entitlement are used to identify and target issues with the existing OPC recipe and to drive continuous improvements to close these performance gaps across the critical design rules. We demonstrate this flow on a 20 nm contact layer.
We continue to study the feasibility of using Directed Self Assembly (DSA) in extending optical lithography for High
Volume Manufacturing (HVM). We built test masks based on the mask datatprep flow we proposed in our prior year’s
publication . Experimental data on circuit-relevant fin and via patterns based on 193nm graphoepitaxial DSA are
demonstrated on 300mm wafers. With this computational lithography (CL) flow we further investigate the basic
requirements for full-field capable DSA lithography. The first issue is on DSA-specific defects which can be either
random defects due to material properties or the systematic DSA defects that are mainly induced by the variations of the
guiding patterns (GP) in 3 dimensions. We focus in studying the latter one. The second issue is the availability of fast
DSA models to meet the full-chip capability requirements in different CL component’s need. We further developed
different model formulations that constitute the whole spectrum of models in the DSA CL flow. In addition to the
Molecular Dynamic/Monte Carlo (MD/MC) model and the compact models we discussed before , we implement a 2D
phenomenological phase field model by solving the Cahn-Hilliard type of equation that provide a model that is more
predictive than compact model but much faster then the physics-based MC model. However simplifying the model might
lose the accuracy in prediction especially in the z direction so a critical question emerged: Can a 2D model be useful fro
full field? Using 2D and 3D simulations on a few typical constructs we illustrate that a combination of 2D mode with
pre-characterized 3D litho metrics might be able to approximate the prediction of 3D models to satisfy the full chip
runtime requirement. Finally we conclude with the special attentions we have to pay in the implementation of 193nm
based lithography process using DSA.
At the 14 nm logic node, significant lithographic changes relative to previous technologies are needed to resolve smaller
features with increased fragmentation in mask design and increased use of sub-resolution assist features. Extending the
application of 193 immersion lithography for further generations requires not only continued reduction of traditional
sources of variation but investigation into and quantification of the impact of completely new ones, such as mask twodimensional
(2D) variability. To improve the overall lithography model accuracy, two-dimensional (2D) data from the
mask is required to complete a mask model with an optimal wafer response. This paper characterizes and assesses the
importance of 2D mask effects on thin opaque MoSi on glass (OMOG) masks. Methodologies for characterizing corner
rounding in terms of corner rounding radius and contact area are presented. Optical mask 2D measurements and wafer
print results are summarized.
To prevent catastrophic failures during wafer manufacturing, mask manufacturers employ sophisticated
reticle inspection systems to examine every image on every reticle to identify defects. These advanced
systems inspect at resolutions typically 3x higher at the reticle-plane than advanced wafer scanners; thus
enabling them to detect the small defects necessary to ensure reticle quality.
The most thorough inspection is done using a reticle-to-database comparison that ensures the reticle pattern
matches the design pattern. For high defect sensitivity, the database must be carefully modeled to exactly
match the reticle pattern. Further, sub-resolution OPC shapes are often at the limit of the mask
manufacturing process, which adds subtle variations on such shapes across the reticle. These modeling
errors and process variations can cause high numbers of unwanted detections, thereby limiting inspection
system defect detection sensitivity.
OPC designs are expected to become more aggressive for future generations and may stress the
performance of current reticle inspection systems. To systematically assess the capability of various
inspection approaches and identify needed areas for improvement, a new “Nightmare” test reticle has been
designed by IBM. The test reticle contains various sizes and shapes of sub-resolution features that might
appear on reticle generations from today’s 22nm to future 7nm. It also contains programmed defects to
assess defect detection capability of current and future generation inspection systems.
This paper will discuss the design of the “Nightmare” test reticle, and the inspection results of the current
generation reticle inspection methods with emphasis on both inspectability and defect sensitivity. The subresolution
features will be ranked according to importance for advanced OPC design. The reticle will also
be evaluated using wafer print simulation so lithographic impact of features and defects can be measured
and compared against inspection approaches and results.
EUV insertion timing for High Volume Manufacturing is still an uncertainty due to source power and EUV mask infrastructure limitations. Directed Self Assembly (DSA) processes offer the promise of providing alternative ways to extend optical lithography cost-effectively for use in the 10nm node and beyond. The goal of this paper is to look into the technical prospect of DSA technology, particularly in the computational and DFM area. We have developed a prototype computational patterning toolset in-house to enable an early Design –Technology Co-Optimization to study the feasibility of using DSA in patterning semiconductor devices and circuits. From this toolset we can identify the set of DSA specific design restrictions specific to a DSA process and plan to develop a novel full chip capable computational patterning solution with DSA. We discuss the DSA Computational Lithography (CL) infrastructure using the via and fin layers as examples. Early wafer data is collected from the DSA testmask that was built using these new toolsets. Finally we discuss the DSA ecosystem requirements for enabling DSA lithography and propose how EDA vendors can play a role in making DSA Lithography (DSAL) a full-chip viable technology for multiple process layers.