Miniature columns or microcolumns are a relatively new class of electron beam columns fabricated entirely from silicon
using advanced micromachining processes. The main characteristics of these columns are thermal field emission (TFE)
sources, low voltage operation (typically <3keV), simple design (two lenses, no crossover), microfabricated lenses, and
all electrostatic components. Current production versions of miniature columns achieve <10nm resolution at 1keV, and
have demonstrated <6nm resolution at higher beam energies.1,2 While this performance is suitable for most applications,
previous studies of the electron optics of miniature electrostatic lenses show better performance should be attainable
under “ideal” conditions.3 In practice, achieving these conditions is challenging because, in addition to the
manufacturing errors from the miniature optics, other subsystems can impose additional constraints. An understanding
of the major contributors to column performance, whether optical or mechanical, is essential, and can provide a roadmap
for further improvements in the existing technology.
The printed circuit board (PCB) industry has long used a lithography process based on a polymer mask in contact with a
large, resist-coated substrate. There is a limit to this technique since both the masks and PCB substrates themselves may
undergo distortion during fabrication, making high resolution or tight registration difficult. The industry has increasingly
turned to digital lithography techniques which, in addition to eliminating the masks, can actively compensate for
distortions. Many of these techniques rely on a "dot-matrix" style exposure technique that uses "binary" pixels and small
pixel or dot spacing to achieve the required resolution. This results in limitations in write speed and throughput, since
many small pixels or dots must be written over a relatively large area PCB substrate. A patented gray level technique1 based on a commercially available digital micro-mirror device (DMD) achieves required resolutions with a relatively
large projected pixel size, and thus offers a higher speed alternative to conventional digital techniques. The technique
described is not limited to PCB, but may be applied to any lithography or printing-based application where high speed
and accurate registration are concerns.
Recently global space charge effects were found to seriously limit the performance of high throughput projection electron beam lithography systems. A fundamental analytical theory describing the global space charge lens has been developed using the variational principle. A modified paraxial ray equation and a set of aberration integrals is derived. All the space charge effects, including the defocus, the magnification variation, and the third order aberrations, are found to be proportional to the perveance, the weighted integrals of the normalized current density distribution, and a combination of the system parameters, such as: the field size and the convergence angle. A simple scaling law for the space charge aberrations, where the aberrations at the image edge scale linearly with the radial dimension, has been found for the telecentric projection configuration. Both the theoretical calculations and the Monte Carlo simulations have been done for a SCALPEL configuration with 25 (mu) A beam current and two scaled systems, whose radial dimensions are scaled from SCALPEL by twice and 3 times, and current by 4 times and 9 times respectively at 10 kV. From both theoretical and simulation results, the space charge aberrations at the edge show approximately a 63 times increase in the twice-scaled system, and about 95 times increase in the three-time-scaled system. All these aberration scaling factors are very close to those predicted from the simple scaling law. An experiment based on the simple scaling law was designed to verify the theory and evaluate the performance of the high throughput projection system. In the scaled testing column which has a 1.6 mA beam current, 5 kV beam voltage, 40 cm column length, 8 mm field diameter, and 4 mrad convergence angle at the mask, the space-charge-aberration blur to be measured will be as large as 200 micrometer. Then the final image blur of the real high throughput system can be derived by using the scaling law.
An inspection system has been developed that uses high-speed electron- beam imaging combined with digital image processing to automatically locate defects on semiconductor wafers. The system inspects wafers using a low beam energy of 0.8 KeV and a scan speed that is as much as 1000 times faster than traditional SEMs. This paper describes the system and presents characterization testing results of the system's ability to find defects on advanced integrated circuits. Three unique applications for the new automated scanning electron microscope inspection system (SEMSpec) have been found. First, the high resolution of the electron imaging microscope allows the tool to find much smaller defects than optical inspection systems can find. The SEMSpec system found defects smaller than 0.1 micrometers in size, even on densely packed, sub-quarter micron, high aspect ratio, multilayer geometries. Second, wafers that are late in the fabrication process are much easier to inspect at high sensitivity by SEMSpec than by optical means. This is because SEMSpec images are much cleaner than optical images when viewing grainy poly, metal, or other interconnect layers. Third, the SEMSpec system can sometimes find electrical problems by observing charge-induced voltage contrast differences. Voltage contrast occurs when some of the IC features are electrically defective and they charge up differently under the electron beam than they normally would. The SEMSpec system can then identify them as defective even though they might otherwise appear to be perfectly formed.