Continuous economic pressures have moved a large percent of integrated device manufacturing (IDM) operations either overseas or to foundry operations over the last 10 years. These pressures have left the IDM fabs in the U.S. with required COO improvements in order to maintain operations domestically. While the assets of many of these factories are at a very favorable point in the depreciation life cycle, the equipment and processes are constrained to the quality of the equipment in its original state and the degradation over its installed life. With the objective to enhance output and improve process performance, this factory and their primary lithography process tool supplier have been able to extend the usable life of the existing process tools, increase the output of the tool base, and improve the distribution of the CDs on the product produced. Texas Instruments Incorporated lead an investigation with the POLARIS<sup>®</sup> Systems & Services business of FSI International to determine the sources of variance in the i-line processing of a wide array of IC device types. Data from the sources of variance were investigated such as PEB temp, PEB delay time, develop recipe, develop time, and develop programming. While PEB processes are a primary driver of acid catalyzed resists, the develop mode is shown in this work to have an overwhelming impact on the wafer to wafer and across wafer CD performance of these i-line processes. These changes have been able to improve the wafer to wafer CD distribution by more than 80 %, and the within wafer CD distribution by more than 50 % while enabling a greater than 50 % increase in lithography cluster throughput. The paper will discuss the contribution from each of the sources of variance and their importance in overall system performance.
Proc. SPIE. 6153, Advances in Resist Technology and Processing XXIII
KEYWORDS: Lithography, Diffractive optical elements, Data modeling, Control systems, Critical dimension metrology, Photoresist processing, Semiconducting wafers, Control systems design, Wafer testing, Temperature metrology
As the lithography community has moved to ArF processing on 300 mm wafers for 90 nm design rules the process characterization of the components of variance continues to highlight the thermal requirements for the post exposure bake (PEB) processing step. In particular as the thermal systems have become increasingly uniform, the transient behavior of the thermal processing system has received the focus of attention. This paper demonstrates how a newly designed and patented thermal processing system was optimized for delivering improved thermal uniformity during a typical 90 second PEB processing cycle, rather than being optimized for steady state performance. This was accomplished with the aid of a wireless temperature measurement wafer system for obtaining real time temperature data and by using a response surface model (RSM) experimental design for optimizing parameters of the temperature controller of the thermal processing system. The new units were field retrofitted seamlessly in <2 days at customer sites without disruption to process recipes or flows. After evaluating certain resist parameters such as PEB temperature sensitivity and post exposure delay (PED) - stability of the baseline process, the new units were benchmarked against the previous PEB plates by processing a split lot experiment. Additional hardware characterization included environmental factors such as air velocity in the vicinity of the PEB plates and transient time between PEB and chill plate. At the completion of the optimization process, the within wafer CD uniformity displayed a significant improvement when compared to the previous hardware. The demonstrated within wafer CD uniformity improved by 27% compared to the initial hardware and baseline process. ITRS requirements for the 90 nm node were exceeded.