In modern photolithography, ever smaller critical dimension (CD) budgets require tighter control over the entire process,
demanding more accurate practice of optical proximity correction (OPC). In last decade, the model based OPC
(MBOPC) has outpaced the rule based OPC (RBOPC) and become widely adopted in semiconductor industry. During
the MBOPC process, the physical models are called to compute the signal values at the evaluation points and the design
patterns are perturbed such that the final model contours are as close to the targets as possible. It has been demonstrated
that in addition to simulating the optics and resist effects, the physical models must accommodate the pattern distortion
due to etch process as well. While the etch process may be lumped with optics and resist processes into one model for
the 65nm and above nodes, it can no longer be treated as small perturbations on photolithographic effects for more
advanced nodes and it is highly desired to build a physics-based etch model formulations that differ from the
conventional convolution-based process models used to simulate the optical and resist effect. Our previous studies
proposed a novel non-linear etch modeling object in combination with conventional convolution kernels, which
simulates the non-optics and non-resist proximity effect successfully. This study examines further the non-linear etch
modeling method by checking the different behaviors of N and p doped layers which physically have different etching
rates and should be represented differently in etch modeling. The experimental results indicate that the fitting accuracy
is significantly improved when the data points are split into N and P groups and calibrated separately. The N and P layer
etch models are used in staged MBOPCs and the results are compared with single-layer model as well.
Although the mask pattern created by fine ebeam writing is four times larger than the wafer pattern, the mask
proximity effect from ebeam scattering and etch is not negligible. This mask proximity effect causes mask-CD errors and consequently wafer-CD errors after the lithographic process. It is therefore necessary to include
the mask proximity effect in optical proximity correction (OPC). Without this, an OPC model can not predict
the entire lithography process correctly even using advanced optical and resist models. In order to compensate
for the mask proximity effect within OPC a special model is required along with changes to the OPC flow.
This article presents a method for producing such a model and OPC flow and shows the difference in results
when they are used.
Emerging resist and etch process technologies for the 45 nm node exhibit new types of
non-optical proximity errors, thus placing new demands on OPC modeling tools. In a
previous paper (SPIE Vol. 6283-75) we had experimentally demonstrated a full resist and
etch model calibration and verified the stability of the model using 45nm node standard
logic cells. The etch model used a novel non-linear etch modeling object in combination
with conventional convolution Kernels. Building upon those results, this paper focuses
on the correction of patterns.
We demonstrate a two-stage optical/resist and etch correction using calibrated models,
including the use of non-linear etch modeling objects. Optical/resist and etch models are
built separately and used sequentially to correct a 45nm logic pattern. Critical areas of
the pattern affected by etch are analyzed and used to verify the correction. Verification
of the correction is obtained through comparison between the simulated contours with the
For the 45nm node and beyond, ever smaller CD budgets require tighter control over the entire process, demanding more accuracy from optical proximity correction (OPC). With the industry adoption of model-based over the traditional rules-based approach, OPC has come a long way to improve accuracy. Today, it is time to do the same for another important step in the process: dry etch. Here we demonstrate the accuracy of etch modeling for a 45nm node process. All experiments were conducted at IMEC with an immersion scanner using off axis illumination. Etch was achieved using a non-optimal recipe to exhibit an iso-dense bias effect. SEM data was extracted using a novel tool to automatically remove any experimental noise. Model calibration was performed with Progen<sup>TM</sup> using standard and novel etch-sensitive structures. Model accuracy and predictability was verified with comparing modeled 2D contours against CD SEM measurements and images.
Negative etch bias is often used to decrease the minimum linewidth beyond what is possible with lithography alone, for example 110 nm minimum CD in resist and 70 nm minimum CD after etch. If the minimum space that can be opened in resist is, for example, 30 nm a true 70 nm half-pitch can be achieved when an etch shrink is employed. Due to iso-dense bias and other proximity effects, however, positive etch bias can also occur. This leads to the unfavorable situation where litho must print lines in resist smaller than the lines in the final post-etch silicon. Due to positive etch bias, among other factors, it is possible to create a configuration that can be realized from the point of view of etch, but can not be created due to photolithography or mask constraints. Specific trouble spots include boundary regions which transition between one set of DRC rules and another. With a new highly accurate etch model, problematic configurations can be identified and used to modify the design to make the etch, photolithography, and mask construction processes realizable. This paper will demonstrate unrealizable pattern conditions that can be found using a non-linear etch model for OPC[R], leading to layout configuration changes which improve the mask construction and photolithography processes.
The challenges of the 65 nm node and beyond require new formulations of the compact convolution models used in OPC. In addition to simulating more optical and resist effects, these models must accommodate pattern distortions due to etch which can no longer be treated as small perturbations on photo-lithographic effects. (Methods for combining optical and process modules while optimizing the speed/accuracy tradeoff were described in “Advanced Model Formulations for Optical and Process Proximity Correction”, D. Beale et al, SPIE 2004.) In this paper, we evaluate new physics-based etch model formulations that differ from the convolution-based process models used previously. The new models are expressed within the compact modeling framework described by J. Stirniman <i>et al.</i> in SPIE, vol. 3051, p469, 1997, and thus can be used for high-speed process simulation during full-chip OPC.
The challenges of the 65 nm node and beyond require new formulations of the compact convolution models used in OPC. In addition to simulating more optical and resist effects, these models must accommodate pattern distortions due to etch which can no longer be treated as small perturbations on photo-lithographic effects. (Methods for combining optical and process modules while optimizing the speed/accuracy tradeoff were described in “Advanced Model Formulations for Optical and Process Proximity Correction”, D. Beale et al, SPIE 2004.) In this paper, we evaluate new physics-based etch model formulations that differ from the convolution-based process models used previously. The new models are expressed within the compact modeling framework described by J. Stirniman <i>et al</i>. in SPIE, vol. 3051, p469, 1997, and thus can be used for high-speed process simulation during full-chip OPC.
As post-litho process effects account for a larger and larger portion of CD error budgets, process simulation terms must be given more weight in the models used for proximity correction. It is well known that for sub-90 nm processes resist and etch effects can no longer be treated as a small perturbation on a purely optical (aerial image) OPC model. The aerial image portion of the model must be combined in a more appropriate way with empirical terms describing resist and etch effects. The OPC engineer must choose a model form which links an optical component with a resist/etch component in a manner that balances efficiency, robustness and fidelity to the aerial image, among other factors. No single way of connecting litho and etch models is ideal in all cases; the best form of linkage depends on the particular litho and etch process to be simulated. In this paper, we provide practical guidelines for linking litho and etch components of a model, using a representative 70 nm process with a large etch bias as an example. This 70 nm case study, which is representative of many sub-90 nm processes that rely on etch to shrink critical features, presents special challenges for OPC modeling. For the process under study, lines were are printed in resist at 120 nm, and the litho model was verified via resist SEM measurements taken at the resist edge. Note that a thresholded aerial image is not well-characterized a distance 25 nm from the resist edge. This is roughly the distance the edge moves back due to the etch step. Although in some cases etch bias can be calculated from aerial image contrast, in general etch bias cannot be predicted from the aerial image because litho and etch are governed by different underlying physics. The model forms available for linking litho and etch range from the efficient “lumped” form, which combines litho and etch simulation in a single model, to a highly accurate two-stage form which separates the two components. In this paper we evaluate the following model forms for applicability to the 70 nm process under study: 1) Aerial image/load kernel combined (“lumped”) model form 2) Aerial image/rule offset “hybrid” model form 3) Separate litho and etch models (2-stage correction)
For low k1 lithography, more aggressive OPC is being applied to critical layers, and the number of mask layers with OPC treatments is growing rapidly. The 130 nm, process node required, on average, 8 layers containing rules- or model-based OPC. The 90 nm node will have 16 OPC layers, of which 14 layers contain aggressive model-based OPC. This escalation of mask pattern complexity, coupled with the predominant use of vector-scan e-beam (VSB) mask writers contributes to the rising costs of advanced mask sets. Writing times for OPC layouts are several times longer than for traditional layouts, making mask exposure the single largest cost component for OPC masks. Lower mask yields, another key factor in higher mask costs, is also aggravated by OPC. Historical mask set costs are plotted below. The initial cost of a 90 nm-node mask set will exceed one million dollars. The relative impact of mask cost on chip depends on how many total wafers are printed with each mask set. For many foundry chips, where unit production is often well below 1000 wafers, mask costs are larger than wafer processing costs. Further increases in NRE may begin to discourage these suppliers' adoption to 90 nm and smaller nodes. In this paper we will outline several alternatives for reducing mask costs by strategically leveraging dimensional margins. Dimensional specifications for a particular masking layer usually are applied uniformly to all features on that layer. As a practical matter, accuracy requirements on different features in the design may vary widely. Take a polysilicon layer, for example: global tolerance specifications for that layer are driven by the transistor-gate requirements; but these parameters over-specify interconnect feature requirements. By identifying features where dimensional accuracy requirements can be reduced, additional margin can be leveraged to reduce OPC complexity. Mask writing time on VSB tools will drop in nearly direct proportion to reduce shot count. By inspecting masks with reference to feature-dependent margins, instead of uniform specifications, mask yield can be effectively increased further reducing delivered mask expense.
Standard industry practice in model-based optical proximity correction is to use a single-stage model in which mask, optical projection, resist, and etch effects are lumped together [J.P. Stirniman, M.L. Rieger, SPIE Proc. Optical/Laser Microlithography X, Vol. 3051, p294, 1997.] Through the 130nm node, where optical projection and resist effects dominated proximity errors, the single-stage model approach has proven to be a convenient, accurate and efficient methodology. A disadvantage of this approach is its lack of modularity. If any one component of the process changes, a new lumped model must be built, usually by shooting a new set of test wafers from which to collect calibration data. Staged correction, in which corrections for different process steps are carried out sequentially, has become an appealing alternative to single-stage correction for the 130 nm node, 100 nm node and beyond. In addition to providing potential "mix and match" capabilities, the component corrections can be better optimized for unique behaviors in the constituent process steps. Thus, the overhead of sequencing through separate corrections can be offset by increased correction efficiency at each step to achieve accuracy equal to, or better than, that of a single stage correction with a lumped model. Separate corrections for etch and for litho/resist have been put into use in the industry and an additional stage for mask correction has also been considered.
In this paper we demonstrate advantages of staged correction over the traditional single-stage correction. Advantages and disadvantages of different staged correction flows will be examined, with particular emphasis on the flow where an etch correction is followed by a lithography correction.
Emerging resolution enhancement techniques (RET) and OPC are dramatically increasing the complexity of mask layouts and, in turn, mask verification. Mask shapes needed to achieve required results on the wafer diverge significantly from corresponding shapes in the physical design, and in some cases a single chip layer may be decomposed into two masks used in multiple exposures. The mask verification challenge is to certify that a RET-synthesized mask layout will produce an acceptable facsimile of the design intent expressed in the design layout. Furthermore costs, tradeoffs between mask-complexity, design intent, targeted process latitude, and other factors are playing a growing role in helping to control rising mask costs. All of these considerations must in turn be incorporated into the mask layout verification strategy needed for data prep sign-off.
In this paper we describe a technique for assessing the lithographic quality of mask layouts for diverse RET methods while effectively accommodating various manufacturing objectives and specifications. It leverages the familiar DRC paradigm for identifying errors and producing DRC-like error shapes in its output layout. It integrates a unique concept of “check figures” - layer-based geometries that dictate where and how simulations of shapes on the wafer are to be compared to the original desired layout. We will show how this provides a highly programmable environment that makes it possible to engage in “compound” check strategies that vary based on design intent and adaptive simulation with multiple checks. Verification may be applied at the “go/no go” level or can be used to build a body of data for quantitative analysis of lithographic behavior at multiple process conditions or for specific user-defined critical features. In addition, we will outline automated methods that guide the selection of input parameters controlling specific verification strategies.
In typical rule- or model-based optical proximity correction (OPC) the goal is to align the silicon layout edges as closely as possible to the corresponding edges in the design layout. OPC precision requirements are approaching 1nm or less at the 0.1mm process node. While state-of-the-art OPC tools are capable of operating at this accuracy, such tight requirements increase computational cycle time, output file size, and photomask fabrication cost. Accuracy requirements on different features in the design may vary widely, and regions that do not need the highest accuracy can be exploited to reduce OPC complexity. For example, transistor gate dimensions require tighter dimensional control than interconnect features on the polysilicon layer. Furthermore gate features typically occupy less area than interconnect. When relaxed OPC accuracy requirements are applied to the interconnect features, but not the gate features, the overall complexity of the polysilicon mask pattern can be significantly reduced without losing accuracy where it counts.
In its purest form optical proximity correction (OPC) creates a mask layout to faithfully reproduce the design intent, or target, on silicon. Practical, production-worthy OPC deviates from this ideal in several respects. First, each set of anticipated process conditions -- defocus, dose -- would require a unique ideal correction. An optimized OPC shape must be derived to minimize harm over the expected ranges of process conditions. Second, the original design layout does not always convey accurate or complete information about the design intent. For example, square corners cannot be printed; how much corner rounding is acceptable? Some legacy design practices, such as line-end extension rules, anticipate (in part) proximity-effects where the intended line end is shorter than drawn. Without additional information, the OPC tool is constrained to aim for the one silicon layout matching the drawn layout as closely as possible. On the other hand, if the OPC tool is given limited liberty to deviate from drawn shapes and positions where they have little or no impact on circuit behavior the correction can be better optimized for several, sometimes competing, constraints - such as: minimizing output figure complexity, minimizing CD error through process variation, maximizing image contrast, and minimizing mask error enhancement factor. In this paper we will demonstrate OPC strategies for optimizing corrections to minimize the harmful effects of random process variations while simultaneously minimizing mask layout complexity. We introduce the concept of a 'conformal target' layout which enhances the drawn pattern with design-intent tolerance information. This information specifies bounds on minimum line and space dimensions, line position, and edge position. Such feature-specific tolerance information provides additional degrees of freedom for OPC synthesis to optimize trade-offs among process window behavior, contrast, MEEF reduction, output figure complexity, and other fab-specific objectives. Furthermore, the tolerance-based conformal target provides an ideal reference pattern for verifying OPC and other resolution enhancement treatments (RET) on the mask layout.