Node to node design rule are shrinking to enable better performance envelope in storage, computing power and electrical usage. A major part of every technology development is verification of the actual device overlay for thick stacks. Today the IC manufactures utilize TEM, Fib and other methods to understand the impact of overlay for thick stacks. These methods, which are considered as a “ground truth” of the fab, can give very good resolution of the features shape characteristics, material contrast, metrology and defectivity. That said, some are destructive and have long time to results. Another approach for thick stack is to use eBeam high kV landing with elluminator technology, this enables fast see through measurements of overlay, yet this approach has also limitation where layer stack thickness exceeds see through imaging capability while chipmakers still require seeing the bottom layer to measure the overlay.
In this paper, we propose a flow of accurate in-line runtime delayer method flowed by an eBeam elluminator technology for overlay verification as an extension of current eBeam measurement capabilities. This flow can be complimentary for different applications space where there’s imaging limitation of the eBeam. The excellent local delayer control enables shorter time to root cause, process and design verification metrology (as a “golden ruler”) in runtime fab.
The work is based on IMEC frontend wafer at source drain Implant process steps after Hard Mask Etch. Looking at device features we explore the accuracy of new flow in sampling fins, dummy gate and Hard mask openings for implant process steps. Reference eBeam metrology will verify the accuracy of the delayer metrology.
As design rules shrink, Critical Dimension Uniformity (CDU) and Line Edge Roughness (LER) constitute a higher percentage of the line-width and hence the need to control these parameters increases. Sources of CDU and LER variations include: scanner auto-focus accuracy and stability, lithography stack thickness and composition variations, exposure variations, etc. These process variations in advanced VLSI manufacturing processes, specifically in memory devices where CDU and LER affect cell-to-cell parametric variations, are well known to significantly impact device performance and die yield. Traditionally, measurements of LER are performed by CD-SEM or Optical Critical Dimension (OCD) metrology tools. Typically, these measurements require a relatively long time and cover only a small fraction of the wafer area. In this paper we present the results of a collaborative work of the Process Diagnostic & Control Business Unit of Applied Materials® and Nikon Corporation®, on the implementation of a complementary method to the CD-SEM and OCD tools, to monitor post litho develop CDU and LER on production wafers. The method, referred to as Process Variation Monitoring (PVM), is based on measuring variations in the light reflected from periodic structures, under optimized illumination and collection conditions, and is demonstrated using Applied Materials DUV brightfield (BF) wafer inspection tool. It will be shown that full polarization control in illumination and collection paths of the wafer inspection tool is critical to enable to set an optimized Process Variation Monitoring recipe.