We present our approach to a low-cost, highly scalable opto-electronic integration platform based on a commercial
CMOS process. In this talk, we detail the performance of the device library elements and highlight performance trade-offs
encountered in monolithically integrating optical and electronic circuits. We describe an opto-electronic integrated
circuit (OEIC) design toolkit modeled after the standard electronic design flow, which includes automated design rule
checking (DRC) and layout-versus-schematic (LVS) checks covering all types of circuit elements. As an example of
integration, we detail the design of a multi-channel transceiver chip with 10 Gbps/channel optical data transmission
speed and report on its performance.
A positive feedback technique is proposed to augment the bandwidth extension achievable using peaking inductors. The technique is based on inductor sharing between consecutive amplifier stages, and it can be effective when used with smaller inductance values compared to traditional inductive peaking. A 40Gb/s two-stage amplifier comprising a differential pair and emitter followers is presented as a practical design example. An expression for the transfer function of the proposed circuit is derived, and its bandwidth and group delay are compared to equivalent amplifiers with inductive peaking and without bandwidth extension. Circuit sensitivity to the inductance value is also considered. The proposed amplifier was implemented in a SiGe BiCMOS process with ƒτ=120GHz and is used as a predriver for a 50Ω buffer. Combined with the buffer, it provides 10dB of gain and consumes 90mW from a 2.5V power supply and 180mW from a 3.3V power supply. Simulations show about 40% bandwidth improvement compared to traditional inductive peaking. Time domain measurements demonstrate 40Gb/s operation with a maximum differential swing of 1.0V p-p and 20-80% transition times of 7-9ps.