VESTIC technology is an alternative for traditional CMOS technology. This paper presents first measurement data of prototypes of VES-BJT: bipolar transistors in VESTIC technology. The VES-BJT is a bipolar transistor on the SOI substrate with symmetric lateral structure and both emitter and collector made of polysilicon. The results indicate that VES-BJT can be a device with useful characteristics. Therefore, VESTIC technology has the potential to become a new BiCMOS-type technology with some unique properties.
A test chip for investigation of junctionless FETs as sub-THz electromagnetic radiation detectors is presented. A number of sensors have been included in the chip designed for production on the SOI substrate. The sensors differ one from one another by the presence of an antenna, transistor layout and doping details. A technology for fabrication of transistors with the self-aligned gate and well-controlled gate to n+ source/drain separation distance has been developed. Results of device simulation and electrical characterization are presented in the paper.
This paper describes the idea of the energy harvester which converts thermal gradient present in environment into
electricity. Two kinds of such devices are proposed and their prototypes are shown and discussed. The main parts of
harvesters are bimetallic spring, piezoelectric transducer or electrostatic transducer with electret. The applied piezomembrane
was commercial available product but electrets was made by authors. In the paper a fabrication procedure of
electrets formed by the corona discharge process is described. Devices were compared in terms of generated power,
charging current, and the voltage across a storage capacitor.
In this study, measurements of resistance of polysilicon resistors with different widths have been done over the whole
surface of the SOI wafers. The obtained results have been used to determine changes in their width, which is equivalent
with shortening of the channel length in the photoli-thography process. By studying the elements distributed across the
wafers it was possible to assess the homogeneity of the MOS transistor gate manufacturing process. the abstract two
lines below author names and addresses.
A study of pH sensitivity of miniature ISFET-type sensors with silicon nitride sensitive layer has been presented. 4 μm
wide SOI FET microsensor process and 100 nm FinFET nanosensor process have been completed with oxygen plasma
treatment. ID(VDS) and gds characteristics of the devices as well as source follower circuit output signal measurements
have been reported. An influence of 1% HF etching of the gate dielectric on pH sensitivity of the sensors has been
described and an explanation of phenomenon of the sensitivity adjustment has been proposed.