Near-field interference lithography is a promising variant of multiple patterning in semiconductor device fabrication
that can potentially extend lithographic resolution beyond the current materials-based restrictions on the
Rayleigh resolution of projection systems. With H2O as the immersion medium, non-evanescent propagation
and optical design margins limit achievable pitch to approximately 0.53λ/nH2O = 0.37λ. Non-evanescent images
are constrained only by the comparatively large resist indices (typically1.7) to a pitch resolution of 0.5/nresist
(typically 0.29). Near-field patterning can potentially exploit evanescent waves and thus achieve higher spatial
resolutions. Customized near-field images can be achieved through the modulation of an incoming wavefront
by what is essentially an in-situ hologram that has been formed in an upper layer during an initial patterned
exposure. Contrast Enhancement Layer (CEL) techniques and Talbot near-field interferometry can be considered
special cases of this approach.
Since the technique relies on near-field interference effects to produce the required pattern on the resist, the
shape of the grating and the design of the film stack play a significant role on the outcome. As a result, it is
necessary to resort to full diffraction computations to properly simulate and optimize this process.
The next logical advance for this technology is to systematically design the hologram and the incident wavefront
which is generated from a reduction mask. This task is naturally posed as an optimization problem, where
the goal is to find the set of geometric and incident wavefront parameters that yields the closest fit to a desired
pattern in the resist. As the pattern becomes more complex, the number of design parameters grows, and the
computational problem becomes intractable (particularly in three-dimensions) without the use of advanced numerical
techniques. To treat this problem effectively, specialized numerical methods have been developed. First,
gradient-based optimization techniques are used to accelerate convergence to an optimal design. To compute
derivatives of the parameters, an adjoint-based method was developed. Using the adjoint technique, only two
electromagnetic problems need to be solved per iteration to evaluate the cost function and all the components
of the gradient vector, independent of the number of parameters in the design.
Source optimization in optical lithography has been the subject of increased exploration in recent years [1-4], resulting in
the development of multiple techniques including global optimization of process window . The performance
advantages of source optimization have been demonstrated through theory, simulation, and experiment. This paper will
emphasize global optimization of sources over multiple patterns, e.g. co-optimization of critical SRAM cells and the
critical pitches of random logic, and implement global source optimization into current resolution enhancement
techniques (RETs). The effect on optimal source due to considering multiple patterns is investigated. We demonstrate
that optimal source for limited patterns does work for a large clip of layout. Through theoretical analysis and
simulations, we explain that only critical patterns and/or critical combinations of patterns determine the final optimal
source; for example those patterns that contain constraints which are active in the solution. Furthermore, we illustrate,
through theory and simulation, that pixelated sources have better performance than generic sources and that in general it
is impossible for generic sources to construct a truly optimal solution. Sensitivity, tool matching, and lens heating issues
for pixelated sources are also discussed in this paper. Finally, we use a RETs example with wafer data to demonstrate the
benefits of global source optimization.
The semiconductor industry faces a lithographic scaling limit as the industry completes the transition to 1.35 NA
immersion lithography. Both high-index immersion lithography and EUV lithography are facing technical
challenges and commercial timing issues. Consequently, the industry has focused on enabling double patterning
technology (DPT) as a means to circumvent the limitations of Rayleigh scaling. Here, the IBM development
alliance demonstrate a series of double patterning solutions that enable scaling of logic constructs by decoupling
the pattern spatially through mask design or temporally through innovative processes. These techniques have been
successfully employed for early 32nm node development using 45nm generation tooling. Four different double
patterning techniques were implemented. The first process illustrates local RET optimization through the use of a
split reticle design. In this approach, a layout is decomposed into a series of regions with similar imaging
properties and the illumination conditions for each are independently optimized. These regions are then printed
separately into the same resist film in a multiple exposure process. The result is a singly developed pattern that
could not be printed with a single illumination-mask combination. The second approach addresses 2D imaging
with particular focus on both line-end dimension and linewidth control . A double exposure-double etch (DE2)
approach is used in conjunction with a pitch-filling sacrificial feature strategy. The third double exposure process,
optimized for via patterns also utilizes DE2. In this method, a design is split between two separate masks such that
the minimum pitch between any two vias is larger than the minimum metal pitch. This allows for final structures
with vias at pitches beyond the capability of a single exposure. In the fourth method,, dark field double dipole
lithography (DDL) has been successfully applied to BEOL metal structures and has been shown to be overlay
tolerant . Collectively, the double patterning solutions developed for early learning activities at 32nm can be
extended to 22nm applications.
The interaction of water with the photoresist film stack is proving to be a key factor in the current generation of 193-nm immersion lithography. Photoresist performance, CD control, optics lifetime, defectivity, overlay and possibly even tool throughput can all be affected by this interaction. Defect control has been an area of increasing concern as the source of the defects can be quite different than that found in conventional dry lithography . Defects can originate from the UPW (Ultra Pure Water) either as particulates or as dissolved solids that precipitate from residual droplets left behind after scanning. Another source of defects can be particulates generated by the immersion fluid as it flows through the exposure tool or as a consequence of water contact with the resist film or resist/topcoat film stack. Recently there have been reports of printable defects due to stains or "watermarks" on the surface of the photoresist . In this report we describe techniques for the visualization of watermarking and particulate formation on a variety of film surfaces. We also describe experiments testing the staining of a variety of water contaminants and additives and their effect on imaging performance. We will also describe the effect of different topcoats on imaging and defectivity in terms of their surface properties.
Immersion Lithography continues to get more and more attention as a possible solution for the 45nm technology node puzzle. In 2005, there has, indeed, been a lot of progress made. It has gone from a laboratory curiosity to being one of the industry's prime contenders for the lithography technology of choice for the 45nm node. Yet a lot of work remains to be done before it's fully implemented into production. Today, there are over a dozen full field immersion scanners in R&D and pilot lines all around the world. The first full field, pre-production "Alpha" version of the ASML Twinscan AT 1150i was delivered to Albany NanoTech in August, 2004. A consortium made up of AMD, IBM, Infineon, and Micron Technology began early evaluation of immersion technology and in December of 2004, the production of the world's first Power PC microprocessor using immersion lithography, processed on this tool, was announced by IBM.
This paper will present a summary of some of the work that was done on this system over the past year. It will also provide an overview of Albany NanoTech, the facility, its capabilities, and the programs in place. Its operating model, which is heavily focused on cooperative joint ventures, is described. The immersion data presented is a review of the work done by AMD, IBM, Infineon Technologies, and Micron Technology, all members of the INVENT Lithography Consortium in place at Albany NanoTech. All the data was published and presented by the authors in much more detail at the 2005 International Symposium on Immersion Lithography, in Bruges, Belgium.
We present a systematic analysis of the imaging performance for a 0.93 numerical aperture (NA) state-of-the-art immersion lithography scanner and we compare this performance to its dry NA=0.93 counterpart. The increased depth of focus (DOF) enabled by immersion lithography presents a set of advantages for semiconductor manufacturing which we explore in this article. First, we show that 0.93 NA immersion prevents, for a 65nm gate-level process, the need for imposing pitch restrictions with an attenuated-PSM solution; something not possible with an equivalent "dry" process. Second, we demonstrate the superior critical dimension uniformity (CDU) of an immersion process in the presence of realistic focus variations typically encountered in semiconductor manufacturing. Third, we confirm that the through-pitch behavior of "wet" and "dry" scanners is well matched, enabling the possibility of transferring optical proximity corrections (OPC) between the two types of lithography scanners. The transferability of OPC is key to enabling a fast insertion of immersion lithography into the manufacturing process for the 65nm and 45nm nodes. Finally, we conclude that, from an imaging perspective, immersion is ready for high-volume manufacturing.
To make immersion lithography a reality in manufacturing, several challenges related to materials and defects must be addressed. Two such challenges include the development of water immersion compatible materials, and the vigorous pursuit of defect reduction with respect to both the films and the processes. Suitable resists and topcoats must be developed to be compatible with the water-soaked environment during exposure. Going beyond the requisite studies of component leaching from films into the water, and absorption of water into the films, application-specific optimization of photoresists and top coats will be required. This would involve an understanding of how a wide array of resist chemistry and formulations behave under immersion conditions. The intent of this paper is to compare lithographic performance under immersion and dry conditions of resists containing different polymer platforms, protecting groups, and formulations. The compatibility of several developer-soluble top-coat materials with a variety of resists is also studied with emphasis on profile control issues. With respect to defects, the sources are numerous. Bubbles and particles created during the imaging process, material remnants from incomplete removal of topcoats, and image collapse as related to resist swelling from water infusion are all sources of yield-limiting defects. Parallel efforts are required in the material development cycle focusing both on meeting the lithographic requirements, and on understanding and eliminating sources of defects. In this paper, efforts in the characterization and reduction of defects as related to materials chemistry and processing effects will be presented.
Immersion lithography has emerged as the leading solution for semiconductor manufacturing for the 45nm node. With the emergence of the first full-field immersion lithography scanners, the technology is getting ready to be inserted in semiconductor manufacturing facilities throughout the world. In the initial implementation phase, the enhanced depth-of-focus provided by immersion will be utilized to mitigate the narrow process window in which leading-edge semiconductor manufacturing has been forced to operate, creating a new set of opportunities.1 The area of defects, however, has remained of critical concern for this technology. It has become clear that the ultimate proof of the readiness of immersion, especially from a defect point of view, must be attained by integrating the immersion process in a production environment. In this paper, we demonstrate that fully functional 90nm PowerPCTM microprocessors have been fabricated using immersion lithography for one of the litho-critical via levels, achieving the goal of confirming that immersion lithography is a viable manufacturing solution. For this demonstration, we utilized the AT1150i (ASML), currently at Albany NanoTech (NY). The system is a 0.75 NA full-field 193nm projection (4x) scanner. We were able to achieve lithographic and overlay performance that exceeded product specifications while achieving a sufficiently low defect count so as to have yielding chips and modules. We have classified the leading types of defects that can be attributed to the immersion process and have assessed their processing impact. Electrical characterization of the integrated devices confirmed full functionality at both wafer final test (WFT) and module test (MT).