This paper discusses mesh refinement methods used to perform Finite Element Analysis (FEA) for vibration based MEMS Energy Harvester. The three types of meshing elements, 1) Linear Hexahedral, 2) Parabolic Hexahedral and 3) Parabolic Tetrahedral, were used in this study. The meshing methods are used to ensure accurate simulation result particularly in stress, and strain analysis obtained, since they are determined by the displacement of each node in the physical structure. The study of the accuracy of an mesh analysis is also known as mesh convergence study which element aspect ratios must be refined consistently. In this paper the dimensions of each elements were also varied in order to investigate the significant of this methods in achieving better ratios of simulation to theoretical results.
Reduction of power dissipations in CMOS circuits needs to be addressed for portable battery devices. Selection of appropriate transistor library to minimise leakage current, implementation of low power design architectures, power management implementation, and the choice of chip packaging, all have impact on power dissipation and are important considerations in design and implementation of integrated circuits for low power applications. Energy-efficient architecture is highly desirable for battery operated systems, which operates in a wide variation of operating scenarios. Energy-efficient design aims to reconfigure its own architectures to scale down energy consumption depending upon the throughput and quality requirement. An energy efficient system should be able to decide its minimum power requirements by dynamically scaling its own operating frequency, supply voltage or the threshold voltage according to a variety of operating scenarios. The increasing product demand for application specific integrated circuit or processor for independent portable devices has influenced designers to implement dedicated processors with ultra low power requirements. One of these dedicated processors is a Fast Fourier Transform (FFT) processor, which is widely used in signal processing for numerous applications such as, wireless telecommunication and biomedical applications where the demand for extended battery life is extremely high. This paper presents the design and performance analysis of a low power shared memory FFT processor incorporating dynamic voltage scaling. Dynamic voltage scaling enables power supply scaling into various supply voltage levels. The concept behind the proposed solution is that if the speed of the main logic core can be adjusted according to input load or amount of processor's computation "just enough" to meet the requirement. The design was implemented using 0.12 μm ST-Microelectronic 6-metal layer CMOS dual- process technology in Cadence Analogue Environment.
The two main sources of power dissipation in CMOS circuits are dynamic and static power dissipation. Static power dissipation is due to leakage current when the transistor is normally off. The improvement in technology scaling has introduced very large subthreshold leakage current, therefore careful design techniques are very important in order to reduce subthreshold leakage current for low power design. Leakage current occurs in both active and standby modes. It is recommended to switch off the leakage current when the circuit is in standby mode, however it is not always possible to shut off the leakage current completely during this mode. Unlike gate leakage, subthreshold leakage cannot be solved by MOS structures nor by introducing new material. One of the feasible solutions is by combinational use of Low-<i>V<sub>t</sub></i> transistors for its high-speed capability and High-<i>V<sub>t</sub></i> transistors for very small leakage current. Multi-Threshold CMOS (MTCMOS) and Variable-Threshold CMOS (VTCMOS) are biasing techniques that uses combinations of different threshold voltage and are suitable for SRAM design. Ideally the larger the threshold level the lower the leakage current, however, one must decide the optimum value of threshold level between the power switch (High-<i>V<sub>t</sub></i> devices) and (Low-<i>V<sub>t</sub></i> devices), as recovery delay tends to increase in higher threshold level. The full paper will discuss the design and performance of SRAM implemented using MTCMOS and VTCMOS biasing techniques. An improved sensing amplifier in the memory cell was incorporated to enhance the circuit performance.
The new MEMS technology has made a major impact on design of RF components. The results that were not possible with current IC technology are made possible with MEMS technology. Researchers are working to replace the off-chip components with on-chip components so as to achieve a single chip receiver. The high Q inductors and capacitors required for designing RF components are the bottleneck in achieving the single chip receiver. The main advantage of direct conversion architecture is fewer components are required for implementations, but there are certain design issues that must be taken care for these implementations to be successfully achieved. In this paper, MEMS components used within RF systems is analysed. The VCO is the most difficult block of RF front-end design having large impact on system performance; so stringent requirements are imposed on VCO phase noise performance. A typical range of MEMS component values are used to design and implementation the VCO.