Control on the order of a nanometer is crucial for present days advanced logic, SRAM, and DRAM integrated circuits (IC). This level of control is necessary to ensure proper functioning of these circuits. In logic and SRAM applications the most important control parameter is the critical dimension of the gate conductor and for DRAM deep trench it is the etch depth. Advanced Process Control (APC) using feedforward and feedback closed loop techniques have been implemented in fabs for over two decades. Up until recently most fabs have used standalone metrology tools exclusively to collect critical wafer parameters. In this paper, a fully integrated TransformaTM Closed Loop (CL) etch system is used to facilitate nanometer gate etch control by enabling, for the first time, real-time feedforward and feedback measurement on a gate etch process.
A PECVD deposited carbon hardmask is combined with dielectric anti-reflective coating (DARC) for the patterning of sub-90nm lines with 248nm lithography. Using this CVD dual layer stack, <1% reflectivity control is demonstrated for both 248nm and 193nm lithography. The film stack is tested with an etch integration scheme to reduce polysilicon gate critical dimension (CD). The dual layer stack can be defined with less than 100nm thick photoresist. Because of the minimal resist required to open the stack, this film stack enables an integration scheme that extends conventional photoresist trim processes up to 70% of the starting line width. In addition to conventional trim process, a resistless carbon mask trim process is investigated to further shrink the gate critical dimension. The results show that the carbon hardmask has greater than 6:1 etch selectivity to polysilicon, enabling the extension of the resist trimming technique to generate sub-30nm structures using 248nm lithography.
Process tolerances for critical dimensions are becoming increasingly severe as lithographic technology drives the minimum integrated-circuit feature size toward 0.1 micrometers and below. In response, Optical Critical Dimension metrology (OCD), an optical-wavelength light-diffraction technique, is currently undergoing an industry-wide evaluation as a fast, accurate, and non-destructive sub-100nm line-width monitor. As such, effective process monitoring requires detailed understanding of the correlation between CD-SEM and the OCD measurements. Correlation in CD measurements between the OCD technique and SEM techniques is investigated in this paper by measuring photo-resist gratings on a polysilicon gate film stack. Intra-grating CD variation is shown to account for scatter in the correlation plot. A positive offset in the correlation is also observed and a mechanism is proposed to account for the discrepancy. Correlation between CD-SEM and OCD is also demonstrated for samples with three different pitch sizes. A qualitative line-profile correlation between cross-section SEM (X-SEM) and OCD is presented for photoresist gratings in a Focus Exposure Matrix (FEM).
Plasma polymerized organosilane resists films have been shown to exhibit high sensitivity to DUV radiation. We have previously demonstrated a 193nm CVD photoresist process in which plasma polymerized methylsilane (PPMS) is patterned via photo-oxidation, dry-developed, converted into silicon dioxide, and then transferred into an underlying Si layer with high selectivity. The PPMS resist exhibits linearity down to a resolution of 130 nm L/S for a 1:1 pitch. We have demonstrated 100 nm Iso-lines at 28 mJ/cm2 dose with 11 percent dose latitude and 600 nm focus latitude. Depths of focus greater than 500 nm have been demonstrated for 160 nm nested L/S.
Thin layer imaging can extend the optical lithography limit down to sub-0.18 micrometers CD with 193 nm wavelength tools. Thin layer imaging can be implemented in a bi-layer approach, in which a patterned thin layer is transferred into an underlying organic planarizing layer. It can also be implemented in a single-layer hardmask process, in which a photodefineable oxide precursor is used to directly pattern a device layer. In the first portion of our study, a plasma polymerized methyl silane (PPMS) bi-layer baseline process has been characterized for photospeed, resolution, and line edge roughness (LER). 1500 angstroms thick organosilane films were patterned by a photo-oxidation process using a 193 nm stepper (NA equals 0.6). The process exhibits photospeeds that are easily tuned from 40 to 100 mJ/cm2 in a well-controlled manner by adjusting the PPMS CVD deposition parameters. The process has demonstrated a resolution of 0.13 micrometers . We show that the total dry-develop process time is critical in determining the lithographic process latitude, photospeed, resolution and LER characteristics. The CVD resist process is most attractive if the thin layer can be directly converted into a thin oxide hard mask, useful for transferring the pattern directly into an underlying device layer. We demonstrate a CVD photoresist process in which patterned PPMS is converted into a silicon dioxide hardmask, and then transferred into underlying amorphous-Si layers with high sensitivity. Using this technique, we have successfully demonstrated 0.15 micrometers resolution amorphous-Si lines.