A pupil optimization was carried out for the M2 layer of the imec N7 (foundry N5 equivalent) logic design. This is exposed as a single print EUV layer. We focused on the printability of the toughest parts of the design: a dense line space grating of 32 nm pitch and a tip-tip grating of 32 nm pitch, tip-to-tip target CD of 25 nm. We found that the pupil optimization can improve both the line space and the tip-to-tip gratings energy latitude and depth of focus. The tip-to-tip target CD can be pushed further, enabling further design scaling.
Classical SEM metrology, CD-SEM, uses low data rate and extensive frame-averaging technique to achieve high-quality SEM imaging for high-precision metrology. The drawbacks include prolonged data collection time and larger photoresist shrinkage due to excess electron dosage. This paper will introduce a novel e-beam metrology system based on a high data rate, large probe current, and ultra-low noise electron optics design. At the same level of metrology precision, this high speed e-beam metrology system could significantly shorten data collection time and reduce electron dosage. In this work, the data collection speed is higher than 7,000 images per hr. Moreover, a novel large field of view (LFOV) capability at high resolution was enabled by an advanced electron deflection system design. The area coverage by LFOV is >100x larger than classical SEM. Superior metrology precision throughout the whole image has been achieved, and high quality metrology data could be extracted from full field. This new capability on metrology will further improve metrology data collection speed to support the need for large volume of metrology data from OPC model calibration of next generation technology. The shrinking EPE (Edge Placement Error) budget places more stringent requirement on OPC model accuracy, which is increasingly limited by metrology errors. In the current practice of metrology data collection and data processing to model calibration flow, CD-SEM throughput becomes a bottleneck that limits the amount of metrology measurements available for OPC model calibration, impacting pattern coverage and model accuracy especially for 2D pattern prediction. To address the trade-off in metrology sampling and model accuracy constrained by the cycle time requirement, this paper employs the high speed e-beam metrology system and a new computational software solution to take full advantage of the large volume data and significantly reduce both systematic and random metrology errors. The new computational software enables users to generate large quantity of highly accurate EP (Edge Placement) gauges and significantly improve design pattern coverage with up to 5X gain in model prediction accuracy on complex 2D patterns. Overall, this work showed >2x improvement in OPC model accuracy at a faster model turn-around time.
This paper summarizes findings for an N5 equivalent M2 (pitch 32) layer patterned by means of SE EUV. Different mask tonalities and resist tonalities have been explored and a full patterning (litho plus etch) process into a BEOL stack has been developed. Resolution enhancement techniques like SRAFs insertion and retargeting have been evaluated and compared to a baseline clip just after OPC. Steps forward have been done to develop a full patterning process using SE EUV, being stochastics and variability the main items to address.
Both local variability and optical proximity correction (OPC) errors are big contributors to the edge placement error (EPE) budget which is closely related to the device yield. The post-litho contact hole healing will be demonstrated to meet after-etch local variability specifications using a low dose, 30mJ/cm<sup>2</sup> dose-to-size, positive tone developed (PTD) resist with relevant throughput in high volume manufacturing (HVM). The total local variability of the node 5nm (N5) contact holes will be characterized in terms of local CD uniformity (LCDU), local placement error (LPE), and contact edge roughness (CER) using a statistical methodology. The CD healing process has complex etch proximity effects, so the OPC prediction accuracy is challenging to meet EPE requirements for the N5. Thus, the prediction accuracy of an after-etch model will be investigated and discussed using ASML Tachyon OPC model.
In the course of assessing OPC compact modeling capabilities and future requirements, we chose to investigate the interface between CD-SEM metrology methods and OPC modeling in some detail. Two linked observations motivated our study:
1) OPC modeling is, in principle, agnostic of metrology methods and best practice implementation.
2) Metrology teams across the industry use a wide variety of equipment, hardware settings, and image/data analysis methods to generate the large volumes of CD-SEM measurement data that are required for OPC in advanced technology nodes.
Initial analyses led to the conclusion that many independent best practice metrology choices based on systematic study as well as accumulated institutional knowledge and experience can be reasonably made. Furthermore, these choices can result in substantial variations in measurement of otherwise identical model calibration and verification patterns.
We will describe several experimental 2D test cases (i.e., metal, via/cut layers) that examine how systematic changes in metrology practice impact both the metrology data itself and the resulting full chip compact model behavior. Assessment of specific methodology choices will include:
• CD-SEM hardware configurations and settings: these may range from SEM beam conditions (voltage, current, etc.,) to magnification, to frame integration optimizations that balance signal-to-noise vs. resist damage.
• Image and measurement optimization: these may include choice of smoothing filters for noise suppression, threshold settings, etc.
• Pattern measurement methodologies: these may include sampling strategies, CD- and contour- based approaches, and various strategies to optimize the measurement of complex 2D shapes.
In addition, we will present conceptual frameworks and experimental methods that allow practitioners of OPC metrology to assess impacts of metrology best practice choices on model behavior.
Finally, we will also assess requirements posed by node scaling on OPC model accuracy, and evaluate potential consequences for CD-SEM metrology capabilities and practices.
Proc. SPIE. 10143, Extreme Ultraviolet (EUV) Lithography VIII
KEYWORDS: Oxides, Metrology, Data modeling, Calibration, Etching, Metals, Resistance, Photoresist materials, Finite element methods, Photomasks, Extreme ultraviolet, Extreme ultraviolet lithography, Optical proximity correction, Semiconducting wafers, Back end of line
Inpria has developed a directly patternable metal oxide hard-mask as a high-resolution photoresist for EUV lithography1. In this contribution, we describe a Tachyon 2D OPC full-chip model for an Inpria resist as applied to an N7 BEOL block mask application.
Extreme ultraviolet (EUV) lithography is crucial to enabling technology scaling in pitch and critical dimension (CD). Currently, one of the key challenges of introducing EUV lithography to high volume manufacturing (HVM) is throughput, which requires high source power and high sensitivity chemically amplified photoresists. Important limiters of high sensitivity chemically amplified resists (CAR) are the effects of photon shot noise and resist blur on the number of photons received and of photoacids generated per feature, especially at the pitches required for 7 nm and 5 nm advanced technology nodes. These stochastic effects are reflected in via structures as hole-to-hole CD variation or local CD uniformity (LCDU). Here, we demonstrate a synergy of film stack deposition, EUV lithography, and plasma etch techniques to improve LCDU, which allows the use of high sensitivity resists required for the introduction of EUV HVM. Thus, to improve LCDU to a level required by 5 nm node and beyond, film stack deposition, EUV lithography, and plasma etch processes were combined and co-optimized to enhance LCDU reduction from synergies. <p> </p>Test wafers were created by depositing a pattern transfer stack on a substrate representative of a 5 nm node target layer. The pattern transfer stack consisted of an atomically smooth adhesion layer and two hardmasks and was deposited using the Lam VECTOR PECVD product family. These layers were designed to mitigate hole roughness, absorb out-of-band radiation, and provide additional outlets for etch to improve LCDU and control hole CD. These wafers were then exposed through an ASML NXE3350B EUV scanner using a variety of advanced positive tone EUV CAR. They were finally etched to the target substrate using Lam Flex dielectric etch and Kiyo conductor etch systems. Metrology methodologies to assess dimensional metrics as well as chip performance and defectivity were investigated to enable repeatable patterning process development. <p> </p>Illumination conditions in EUV lithography were optimized to improve normalized image log slope (NILS), which is expected to reduce shot noise related effects. It can be seen that the EUV imaging contrast improvement can further reduce post-develop LCDU from 4.1 nm to 3.9 nm and from 2.8 nm to 2.6 nm. In parallel, etch processes were developed to further reduce LCDU, to control CD, and to transfer these improvements into the final target substrate. We also demonstrate that increasing post-develop CD through dose adjustment can enhance the LCDU reduction from etch. Similar trends were also observed in different pitches down to 40 nm. The solutions demonstrated here are critical to the introduction of EUV lithography in high volume manufacturing. It can be seen that through a synergistic deposition, lithography, and etch optimization, LCDU at a 40 nm pitch can be improved to 1.6 nm (3-sigma) in a target oxide layer and to 1.4 nm (3-sigma) at the photoresist layer.
Process-window (PW) evaluation is critical to assess the lithography process quality and limitations. Usual CD-based PW gives only a partial answer. Simulations such as Tachyon LMC (Lithography Manufacturability Check) can efficiently overcome this limitation by analyzing the entire predicted resist contours. But so far experimental measurements did not allow such flexibility. This paper shows an innovative experimental flow, which allows the user to directly validate LMC results across PW for a select group of reference patterns, thereby overcoming the limitations found in the traditional CD-based PW analysis. To evaluate the process window on wafer more accurately, we take advantage of design based metrology and extract experimental contours from the CD-SEM measurements. Then we implement an area metric to quantify the area coverage of the experimental contours with respect to the intended ones, using a defined “sectorization” for the logic structures. This ‘sectorization’ aims to differentiate specific areas on the logic structures being analyzed, such as corners, line-ends, short and long lines. This way, a complete evaluation of the information contained in each CD-SEM picture is performed, without having to discard any information. This solution doesn’t look at the area coverage of an entire feature, but uses a ‘sectorization’ to differentiate specific feature areas such as corners, line-ends, short and long lines, and thus look at those area coverages. An assessment of resist model/OPC quality/process quality at sub nm-level accuracy is rendered possible.
While waiting for EUV lithography to become ready for adoption, we need to create designs compatible with both EUV single exposures as well as with 193i multiple splits strategy for technology nodes 7nm and below needed to keep the scaling trend intact. However, the standard approach of designing standard cells in two-dimensional directions is no more valid owing to insufficient resolution of 193-i scanner. Therefore, we propose a standard cell design methodology, which exploits purely one-dimensional interconnect.
The image border is a pattern free dark area around the die on the photomask serving as transition area between
the parts of the mask that is shielded from the exposure light by the Reticle Masking (ReMa) blades and the die.
When printing a die at dense spacing on an EUV scanner, the reflection from its image border overlaps with the
edges of neighboring dies affecting CD and contrast in this area. This is related to the fact that EUV absorber
stack has 1-3% reflectance for actinic light. For a 55nm thick absorber the induced CD drop at the edges is
found to be 4-5 nm for 27 nm dense lines. In this work we will show an overview of the absorber reflection
impact on CD at the edge of the field across EUV scanner generations, for several imaging nodes and multiple
Increasing spacing between dies on the wafer would prevent the unwanted exposure but results in an
unacceptable loss of valuable wafer real estate thereby reducing the yield per wafer and is thus not a viable
manufacturing solution. In order to mitigate the reflection from the image border one needs to create a so called
black border. The most promising approach is removal of the absorber and the underlying multilayer down to
the low reflective LTEM substrate by multilayer etching. It was shown in the previous study that the impact
on CD was reduced essentially for 27 nm dense lines exposed on ASML NXE:3100.
In this work we will continue the study of a multilayer etched black border impact on imaging. In particular, 22
nm lines/spaces imaging on ASML NXE:3300 EUV scanner will be investigated in the areas close to the black
border as well as die to die effects. We will look closer into the CD uniformity impact by DUV Out-of-Band
light reflected from black border and its mitigation. A possible OPC approach will also be evaluated.
Computational lithography has become indispensable when developing lithography solutions for advanced technology nodes. One of the essential instruments for optimizing full-chip process windows (PW) is source mask optimization (SMO). To avoid model calibration for each new optimized source, separable resist models need to be created such that a reliable model can be obtained simply by replacing the source in the existing OPC model. In this paper we start from a fully calibrated resist model and optimize a new source for which we want to create a reliable OPC model. Relying on the separability of the model, the initial illumination source is replaced by the new one while not changing any resist model parameters. In order to reach the accuracy needed for OPC, the best focus and best dose still need to be accurately determined. We will investigate two models that have the same new SMO source and original resist model. For one model the best focus and dose are determined by the simulated Bossung plot of one anchor feature. The second model’s best focus and exposure are determined by a small set of FEM experimental data. The quality of these two models is then evaluated by comparing them to a reference model, which is fully calibrated using a complete dataset for the new source. We show that the calibrated FEM OPC model can be extrapolated by simply changing the source. A limited amount of experimental FEM data is required to accurately determine the best focus and exposure for the new source. Best focus and exposure based on the anchor pattern simulation has a higher degree of uncertainty compared to a small set of experimental data.
As Extreme Ultraviolet Lithography (EUVL) enters the pre-production phase, the need to qualify the Electronic Design
Automation (EDA) infrastructure is pressing. In fact, it is clear that EUV will require optical proximity correction
(OPC), having its introduction shifted to more advanced technology nodes. The introduction of off-axis illumination will
enlarge the optical proximity effects, and EUV-specific effects such as flare and shadowing have to be fully integrated in
the correction flow and tested.
We have performed a model calibration exercise on the ASML NXE:3100 pre-production EUVL scanner using Brion's
Tachyon NXE EUV system. A model calibration mask has been designed, manufactured and characterized. The mask
has different flare levels, as well as model calibration structures through CDs and pitch. The flare modulation through
the mask is obtained by varying tiling densities. The generation of full-chip flare maps has been qualified against
experimental results. The model was set up and calibrated on an intermediate flare level, and validated in the full flare
Wafer data have been collected and were used as input for model calibration and validation. Two-dimensional structures
through CD and pitch were used for model calibration and verification. We discuss in detail the EUV model, and analyze
its various components, with particular emphasis to EUV-specific phenomena such as flare and shadowing.
Proc. SPIE. 7545, 26th European Mask and Lithography Conference
KEYWORDS: Lithography, Electron beam lithography, Electron beams, FT-IR spectroscopy, Polymethylmethacrylate, Hydrogen, Scanning electron microscopy, Absorbance, Line edge roughness, Photoresist processing
The FP7 European project MAGIC  aims at designing a multi electron beam machine. In the frame of this project,
LETI evaluates a multibeam tool from MAPPER lithography . Each beam has an acceleration voltage of 5kV. A tool
has been installed in LETI premises in July 2009. In order to prepare its evaluation, preliminary work was performed on
Gaussian beam tools down to 5kV. It aimed at the determination of a stable and robust resist process allowing high
resolution at 5kV. Then those results were used to characterize MAPPER tool performances. Meeting the requirements
of high resolution and low roughness at low voltage, Dow Corningmolecular glass HSQ (hydrogen silsesquioxane)
and MicroChem PMMA (polymethylmethacrylate) were used to test MAPPER tool as negative and positive tone resist
references. We did exposures at beam acceleration voltages from 5 kV up to 100 kV. Different post application bake
(PAB) temperatures were applied to resist. Several developer concentrations were also tested. The impact of those three
parameters on contrast and resolution was checked. Resists chemical characterization was performed with FTIR (Fourier
transform infra red) spectroscopy in order to understand the mechanisms leading to the observed variations of contrast
and exposure dose as process parameters are changed. The main purpose of this work was to show that high resolution
can be achieved at 5kV. First exposures performed with MAPER tool confirmed those results.
E-beam Maskless activities raised a lot of interest in the past years from semiconductor
companies strongly concerned by the constant cost increase of masked-based lithography (1).
Beginning of 2008, the European Commission started an integrated program called "MAGIC",
Maskless lithography for IC manufacturing, which pushes the development and the insertion
of the European multi-beam technology (2) in the semiconductor industry. This project
supports also to develop the infrastructure for the use of this technology, including resist
processes, data processing and proximity corrections.
Within MAGIC, MAPPER develops its low energy (5keV) massively parallel concept (3).
Compared to a standard single E-Beam machine working classically at 50kV, this low
accelerating voltage requires the use of thin resist film to deal with the lower penetration
depth of the electrons. This paper presents the resist development status, including
Chemically Amplified Resist and non-CAR platforms. Comparisons of the performances of
these resist platforms in terms of resolution, sensitivity, roughness and stability are detailed,
including their potential integration into CMOS technological flow. Finally, a first review of the
state of the art of resist performance for patterning at 5kV will be performed. Based on the
level of achievements presented in this paper, a discussion is also engaged about the needs
of resist developments to fulfill industry targets in 2011.