Proc. SPIE. 9674, AOPC 2015: Optical and Optoelectronic Sensing and Imaging Technology
KEYWORDS: Readout integrated circuits, Signal to noise ratio, Digital signal processing, Capacitors, Interference (communication), Capacitance, Signal processing, High dynamic range imaging, Analog electronics, Digital electronics
The charge packet readout integrated circuit (ROIC) technology for the IRFPAs is introduced, which can realize that every pixel achieves a very high capacity of the electrons storage, and it also improves the performance of the SNR and reduces the saturation possibility of the pixels. The ROIC for the LWIR requires ability that obtaining high capacity for storing electrons. For the conventional ROIC, the maximum charge capacity is determined by the integration capacitance and the operating voltage, it can achieve a high charge capacity through increasing the area of the integration capacitor or raising the operating voltage. And this paper would introduce a digital method of ROIC that can achieve a very high charge capacity. The circuit architecture of this approach includes the following parts, a preamplifier, a comparator, a counter, and memory arrays. And the maximum charge capacity of the pixel is determined by the counter bits. This new method can achieve a high charge capacity more than 1Ge- every pixel and output the digital signal directly, while that of conventional ROIC is less than 50Me- and output the analog signal from the pixel. In this new circuit, the comparator is a important module, as the integration voltage value need compare with threshold voltage through the comparator all the time during the integration period, and we will discuss the influence of the comparator. This work design the circuit with the CSMC 0.35um CMOS technology, and the simulation use the spectre model.
A 640×512 readout integrated circuit (ROIC) with 15um pixel pitch for middle-wave infrared focal plane arrays (MWIR FPAs) is designed in this paper. The 15um pixel pitch presents several challenges to the ROIC design, such as achieving the required charge storage capacity to preserve the high SNR and reading or processing the pixel signals correctly to achieve the required frame rate. A novel structure that four neighboring pixels share one integration capacitor is presented as a feasible approach to getting a large charge capacity in the limited pixel area. Meanwhile, the pixel circuit chooses the direct injection (DI) which occupies the small layout area as the input stage for MW and contains two sample and hold modules to further increase the charge capacity. Moreover,the peripheral analog signal chain circuit, which is composed of a PMOS source follower, a column amplifier and the complementary output stage, is designed to transfer the signals from unit cell with less voltage loss,lower power consumption, lower noise and higher linearity. More importantly, in our design, only half chain circuit are required therefore the corresponding power consumption will be reduced greatly. In order to accommodate this design, two kinds of pixel signal readout sequences are compared. By adopting the 0.18um 1P6M mixed signal CMOS process, the circuit architecture can make the effective charge capacity of 13Me- per pixel with 1.38V final output range. The 4×4 circuit layout will be fulfilled as a whole and in this way the effective integration capacitor can be increased. According to the simulation results, this circuit works well under 3.3V power supply and achieves 10MHZ readout rate and less than 0.1% nonlinearity.
The high-speed and high dynamic range readout circuits can realize a good performance that achieving intra-scene wide dynamic range，and the readout circuits could get more details of a target view that include very dark and very bright signal. A new architecture of readout circuits with high speed and high dynamic range is introduced. In order to achieve high dynamic range, we use a special architecture of readout circuits. The circuits allow the very high signal to input, and output the signal without damaging. The input stage use a CTIA architecture in the circuits, and connect a feedback circuit and a S/H circuit in the output of CTIA. The architecture of the feedback is a circuit to control the reset switch of CTIA, when a strong signal inputing, the feedback circuit judge the signal of output, if the signal over the reference signal that have been set, the feedback circuit output a reset signal, the output of CTIA is reset to the initial state. A counter records the reset signal, and get the total times of reset. At the last stage of integration period，the S/H circuit samples the signal and a integration period is over. As the circuits could realize multiple reset, the signal would never reach saturation state, and it can achieve a very high range in the output. We use the GLOBALFOUNDRIES 0.35μm technology and simulate the designed circuits with Cadence IC, and test the functions, then analyze the performance of the circuits from the results.
Since the technology trend of the third generation IRFPA towards resolution enhancing has steadily progressed,the pixel pitch of IRFPA has been greatly reduced.A 640×512 readout integrated circuit(ROIC) of IRFPA with 15μm pixel pitch is presented in this paper.The 15μm pixel pitch ROIC design will face many challenges.As we all known,the integrating capacitor is a key performance parameter when considering pixel area,charge capacity and dynamic range,so we adopt the effective method of 2 by 2 pixels sharing an integrating capacitor to solve this problem.The input unit cell architecture will contain two paralleled sample and hold parts,which not only allow the FPA to be operated in full frame snapshot mode but also save relatively unit circuit area.Different applications need more matching input unit circuits. Because the dimension of 2×2 pixels is 30μm×30μm, an input stage based on direct injection (DI) which has medium injection ratio and small layout area is proved to be suitable for middle wave (MW) while BDI with three-transistor cascode amplifier for long wave(LW). By adopting the 0.35μm 2P4M mixed signal process, the circuit architecture can make the effective charge capacity of 7.8Me- per pixel with 2.2V output range for MW and 7.3 Me- per pixel with 2.6V output range for LW. According to the simulation results, this circuit works well under 5V power supply and achieves less than 0.1% nonlinearity.