Dr. Dean N. Truong
Senior Design Engineer at
Area of Expertise:
Manycore and Massively Parallel Processing Array Architecture , Variation-aware Adaptive and Dynamic Voltage and Frequency Scaling , RTL Engineering , Digital Signal Processing , Digital IC Design , Biomedical Signal and Image Processing
Profile Summary

Natural born U.S. Citizen finishing up a Ph.D. in Electrical and Computer Engineering focusing on the application of dynamic voltage and frequency scaling with a manycore platform architecture for biomedical signal and image processing applications.

To be part of a state-of-the-art research/engineering group in the areas of embedded systems (e.g. real-time communications and multimedia front/back-end), high performance computing (e.g. Exascale computing), and/or biomedical signal, image, and video processing (e.g. medical ultrasound).

Primary Experience:
+ RESEARCH ASSISTANT with 16 authored and co-authored papers in top circuits journals and conferences, including IEEE Journal of Solid State Circuits, VLSI Symposium on Technology and Circuits, IEEE Transactions on Circuits and Systems, HotChips Symposia on High Performance Processors, and ACM/IEEE Design Automation Conference.
+ MANYCORE PLATFORM LEAD ARCHITECT working with a team of 10 M.S. and Ph.D. students on a 167-core globally asynchronous and locally synchronous (GALS) array consisting of 164 DSP processors, three application-specific processors (accelerators), and three 16 KB scratchpad shared memories. Design to tape-out completed in 9 months on 65 nm CMOS. The platform is capable of up to 200 GOPS at nominal Vdd, with peak energy-efficiency at 200 GOPS/W at near-threshold operation.

+ Variation-aware Adaptive and Dynamic Voltage and Frequency Scaling (DVFS)
Floorplanning/Layout, Circuits and System Architecture on Manycore Platforms
+ Digital Systems and Computer Architecture
+ RTL Engineering
+ Back-end Design and Verification
+ Digital IC Design
+ Source-synchronous Interconnects
+ Lab Instrumentation & Chip Testing
+ Embedded Software Development
+ LDPC Decoder Architectures
+ Medical Ultrasound Imaging on Massively Parallel Processor Arrays (MPPA)
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