CMOS optical sensors performances are mainly driven by the quantum efficiency and the pixel cross talk. Microlens arrays implementation is a way to improve both by focalizing the incident light on the active photodiode area. Further optimizations include fill factor maximization by reducing the space between microlenses.
In this study we propose the fabrication of zero gap microlens arrays by plasma etch transfer of reflowed microlenses into a subjacent resist layer. The impact of lithography, reflow and etch process parameters on microlenses shape and space reduction are discussed. We show that etch time increase allows gap reduction down to zero, while polymerization control is key to conserve microlens height.
The impact of 3 process factors on the final microlens shape are studied using DOE (design of experiment) methodology. Thus, microlenses gap and height evolution as a function of mask thickness, polymerizing gas flow and etch time are modeled within the experimental range of these factors. An optimum process point is then proposed to minimize the gap while keeping constant the microlens height.
We report on the co-integration of an additional passive layer within a Silicon Photonic chip for advanced passive devices. Being a CMOS compatible material, Silicon Nitride (SiN) appears as an attractive candidate. With a moderate refractive index contrast compared to SOI, SiN based devices would be intrinsically much more tolerant to fabrication errors while keeping a reasonable footprint. In addition, it's seven times lower thermo-optical coefficient, relatively to Silicon, could lead to thermal-tuning free components. The co-integration of SiN on SOI has been explored in ST 300mm R and D photonic platform DAPHNE and is presented in this paper. Surface roughness of the SiN films have been characterized through Atomic Force Microscopy (AFM) showing an RMS roughness below 2nm. The film thickness uniformity have been evaluated by ellipsometry revealing a three-sigma of 21nm. Statistical measurements have been performed on basic key building blocks such as SiN strip waveguide showing propagation loss below 0.7dB/cm and 40μm radius bends with losses below 0.02dB/90°. A compact Si-SiN transition taper was developed and statistically measured showing insertion losses below 0.17dB/transition on the whole O-band wavelength range. Moreover, advanced WDM devices such as wavelength-stabilized directional couplers (WSDC) have been developed.
As geometrical dimensions of semiconductor devices decrease, the need to introduce Cu processes into the fabrication cycle becomes increasingly important as a means of maintaining line resistances and circuit time constants. However, the success of implementing such as fabrication process is dependent on the ability to characterize it through quantitative means, such as Overlay metrology. In this paper we examine the overlay measurement results which have been obtained on a Cu based CMOS process at the 0.12 (Mu) m technology node. Overlay measurements were taken over a wide range of process conditions, and included wafers exhibiting extreme image contrast reversal, grainy conditions and low contrast. These factors have traditionally led to a decreased ability to make repeatable measurements, if the measurements could be made at all. Our results cover the important metrics of overlay metrology, and include precision, recipe portability, and measurement success rates. The results suggest that the overlay metrology issues encountered with such leading edge processes need not pose intractable barriers to obtaining reliable overlay metrology data.
As the number of varied devices produced by a fab increase, coupled with an increased complexity in those devices which call for an ever increasing number of process layers, in- line process control via metrology can become an impossible task, unless metrology recipe management schemes are implemented. Logic fabs are now introducing more than 1 new device per day, which can result in the writing and management of thousands of recipes, which in turn can lead to the costly consumption of tool and personnel resources sand a general loss in productivity. In this paper we present the productivity gains to be made in the recipe creation process through off-line recipe generation, as well as a method of decreasing the recipe optimization time. We will also outline the concept of Just In Time recipe creation, its contribution to productivity gains, and its generalized implementation with respect to Overlay Metrology recipes.