Chip size as a function of field fill on wafer layouts, and their effect on thruput, has been well understood as a loss of both opportunity and cost of operation (COO), as a function of depreciated capital expense. The resultant effects on consumable replacement time, expense and budgeting has not been as clear-cut. This paper will outline the consequences that field fill has with respect to increased laser, and litho tool optic train, consumable usages as well as availability detractors to replace these components. Resulting losses due to increased cost of operation, and additional
consumable spending and usages will be explored.
With the reduce cycle times required to produce customized chips to the end user, the inherent overhead time that is involved with running small lots or even send ahead wafers need to be minimized and optimized to provide reasonable levels of raw throughput. By understanding the process, from the completion of one lot to the start of the next, measurements and actions can be undertaken to outline improvements in the process.