In this work, we reported the buffers optimum of high-quality InP epilayer grown on GaAs substrate for fabrication of InP-related devices. First, LT-GaAs (450°C, 15nm)/LT-InP((450°C, 15nm) double LT buffers were deposited on the substrate as the initial layers. The effects of double LT buffers were studied compared with the results of single LT-InP buffer scheme. It was demonstrated that: (i) with a proper LT-GaAs buffer thickness, the double
LT-buffer became more "compliant" for strain accommodation than single LT-InP buffer; (ii) there existed an optimal thickness of
LT-GaAs buffer for a given thickness of LT-InP layer at which the crystal quality reached the best, just like the conventional buffer optimum process. Second, in order to block the "escaped" dislocations from the buffer/substrate interface, InxGa1-xP/InP (x≈0.2) strained superlattices (SLS) were introduced as defect filtering layers before the growth of the final InP layer. We investigated the effects of the periods and inserting position of the SLS on the stress relaxation and the crystal quality of InP top layer. It was suggested that when the total thickness of the epilayer was fixed, both the thickness and the periods and the distance from the interface should be carefully designed to reduce the stress and improve the crystal quality of the epilayer simultaneously. Finally, a 2-μm-thick InP epilayer was grown on GaAs substrate using (450°C, 15nm)/LT-InP(450°C, 15nm) double LT buffers combined with inserting 15-period (4nm/6nm) In0.8Ga0.2P/InP SLS into epilayer. Then X-ray diffraction measurements showed the best result of the full width at half maximum (FWHM) was 203 arcsec with estimated dislocation density of 2.8×107 cm-2.
Abstract: We have explored the shared-layer integration fabrication of an resonant-cavity-enhanced
p-i-n photodector (RCE- p-i-n-PD) and a single heterojunction bipolar transistor (SHBT) with the
same epitaxy grown layer structure. MOCVD growth of the different layer structure for the GaAs
based RCE- p-i-n-PD/SHBT require compromises to obtain the best performance of the integrated
devices. The SHBT is proposed with super-lattice in the collector, and the structure of the base
and the collector of the SHBT is used for the RCE. Up to now, the DC characteristics of the
integrated device have been obtained.
Two-step growth method was used to grow InP epilayers directly on GaAs (001) substrates. By employing double-crystal x-ray diffraction (XRD) to characterize the epilayers and analyzing the value of full width at half maximum (FWHM) of ω scan rocking curve, we found the initial buffer layer act a key role on the quality of epilayers. Depending on optimizing the thickness and growth temperature of the initial buffer layers, we have succeeded in improving the crystallinity of InP epilayers. When the low temperature buffer layer was 10 nm thickness and grown at 450°C, the quality of InP epilayers for 1μm thickness were the best, its FWHM of XRD ω scan rocking curve was only 512 arcsec and 201arcsec for ω-2θ scans, the room temperature photoluminescence spectrum shows the band edge transition of InP, its central wavelength is 921nm and the FWHM is only 38 meV.These results indicate high quality of InP epilayers on GaAs substrates.